Semiconductor chip and method for manufacturing a semiconductor chip

• US 8,526,476 B2
• Filed: 04/24/2008
• Issued: 09/03/2013
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: OSRAM OLED GMBH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: Engl, Karl, Hoeppel, Lutz, Eichler, Christoph, Sabathil, Matthias, Weimar, Andreas
• Primary Examiner(s): Stultz, Jessica
• Assistant Examiner(s): King, Joshua
• Application Number:
  US12/598,747
• Publication Number:
  US 20100208763A1
• Time in Patent Office: 1,958 Days
• Field of Search: 372/46.012, 372/46.01, 372/46.011, 372/46.013, 257/91, 257/98
• US Class Current: 372/46.01
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/387 with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/0234 Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
• CPC Class Codes: H01S 5/04253 having specific optical properties, e.g. transparent electrodes
• CPC Class Codes: H01S 5/04256 characterised by the configuration
• CPC Class Codes: H01S 5/11 Comprising a photonic bandgap structure
• CPC Class Codes: H01S 5/18308 having a special structure for lateral current or light confinement
• CPC Class Codes: H01S 5/18347 Mesa comprising active layer
• CPC Class Codes: H01S 5/1835 Non-circular mesa
• CPC Class Codes: H01S 5/18369 based on dielectric materials
• CPC Class Codes: H01S 5/18391 Aperiodic structuring to influence the near- or far-field distribution
• CPC Class Codes: H01S 5/3095 Tunnel junction

Abstract

A semiconductor chip with a semiconductor body has a semiconductor layer sequence with an active region provided for generating radiation. A mirror structure that includes a mirror layer and a dielectric layer that is arranged at least in regions between the mirror layer and semiconductor body is arranged on the semiconductor body.

Claims

1. A semiconductor chip comprising:

a semiconductor body comprising a semiconductor layer sequence with an active region provided for generating radiation;

a mirror structure arranged on the semiconductor body, the mirror structure comprising a mirror layer and a dielectric layer structure arranged at least in regions between the mirror layer and the semiconductor body, wherein the dielectric layer structure has at least one cutout; and

a contact structure arranged in the at least one cutout of the dielectric layer structure, wherein the contact structure comprises a reflector layer that contains a metal or a metallic alloy and is arranged closer to the semiconductor body than the mirror layer, and wherein the contact structure comprises a layer containing a transparent conductive oxide material, said layer containing transparent conductive oxide material being arranged in the at least one cutout between the semiconductor body and the reflector layer, wherein the transparent oxide material and the reflector layer are arranged only in the at least one cutout.

2. The semiconductor chip according to claim 1, wherein the dielectric layer structure comprises a plurality of dielectric layers forming a dielectric mirror structure.

3. The semiconductor chip according to claim 1 wherein the semiconductor body has a side face that bounds the semiconductor body in a lateral direction and wherein the dielectric layer structure extends in the lateral direction at least in regions beyond the side face that bounds semiconductor body.

4. The semiconductor chip according to claim 1, wherein the dielectric layer structure is divided into at least two separate subregions by means of the at least one cutout.

5. The semiconductor chip according to claim 1, wherein the contact structure is formed with multiple layers.

6. The semiconductor chip according to claim 1, further comprising a further contact structure arranged on a surface of the semiconductor body, on a side of the active region facing away from the contact structure, wherein the surface is flat in a region laterally adjoining the further contact structure, the surface having a structuring in a further region adjoining the flat region of the surface.

7. The semiconductor chip according to claim 1, wherein the semiconductor chip comprises a carrier, wherein the dielectric layer structure is arranged between the semiconductor body and the carrier.

8. The semiconductor chip according to claim 1, wherein the semiconductor chip comprises a carrier, the semiconductor body being arranged on the carrier, and wherein the dielectric layer structure

comprises a plurality of dielectric layers,

is arranged between the carrier and the semiconductor body,

extends in a lateral direction at least in regions beyond a side face of the semiconductor body that bounds the semiconductor body in the lateral direction,

comprises a cutout;

and

is divided into at least two separate subregions by means of the cutout.

9. The semiconductor chip according to claim 2, wherein the dielectric mirror structure is divided by means of the at least one cutout into an inner subregion and an outer subregion, wherein

the contact structure that is arranged in the at least one cutout of the dielectric layer structure is arranged on the semiconductor body,

a further contact structure is arranged on the semiconductor body on a side of the active region facing away from the contact structure, and

the inner subregion overlaps the further contact structure in a plan view onto the semiconductor chip.

10. The semiconductor chip according to claim 1, wherein the semiconductor chip is embodied as an LED chip, or as a semiconductor laser chip.

15. The semiconductor chip according to claim 2, wherein the dielectric mirror structure is divided by means of the at least one cutout into an inner subregion and an outer subregion, wherein

the contact structure that is arranged in the at least one cutout of the dielectric mirror structure is arranged on the semiconductor body,

a further contact structure is arranged on the semiconductor body on a side of the active region facing away from the contact structure, and

the inner subregion overlaps the further contact structure in a plan view onto the semiconductor chip.

16. The semiconductor chip according to claim 1, wherein the dielectric layer structure is in direct contact with the semiconductor body comprising the semiconductor layer sequence and that the layer containing the transparent conductive oxide material is in direct contact with the semiconductor body comprising the semiconductor layer sequence.

17. The semiconductor chip according to claim 2, wherein the dielectric mirror structure is configured as a Bragg mirror.

11. A method for manufacturing a semiconductor chip the method comprising:

providing a semiconductor layer structure system with an active region provided for generating radiation;

forming a mirror structure over the semiconductor layer structure system, wherein the mirror structure comprises a dielectric layer structure and a mirror layer, wherein the dielectric layer structure has a at least one cutout;

forming a semiconductor body with a layer sequence from the semiconductor layer structure system; and

forming a contact structure in the at least one cutout of the dielectric layer structure, wherein the contact structure comprises a reflector layer that contains a metal or a metallic alloy and is arranged closer to the semiconductor body than the mirror layer, and wherein the contact structure comprises a layer containing a transparent conductive oxide material, said transparent conductive oxide material-containing layer being arranged in the at least one cutout between the semiconductor body and the reflector layer, wherein the transparent oxide material and the reflector layer are arranged only in the at least one cutout.

12. The method according to claim 11, further comprising a surface of the semiconductor body chemically and/or mechanically smoothed in a region.

13. The method according to claim 12, wherein the contact structure is formed over the smoothed region.

14. The method according to claim 13, further comprising forming a further contact structure over the semiconductor body.