Shift register and display device and driving method thereof

• US 8,526,567 B2
• Filed: 10/04/2010
• Issued: 09/03/2013
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun
• Primary Examiner(s): Lam, Tuan T
• Application Number:
  US12/897,360
• Publication Number:
  US 20110085635A1
• Time in Patent Office: 1,065 Days
• Field of Search: None
• US Class Current: 377/64
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0417 Special arrangements specific to the use of low carrier mobility technology
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Abstract

The power consumption of a shift register or a display device including the shift register is reduced. A clock signal is supplied to a shift register by a plurality of wirings, not by one wiring. Any one of the plurality of wirings supplies a clock signal in only part of the operation period of the shift register, not during the whole operation period of the shift register. Therefore, the capacity load caused with the supply of clock signals can be reduced, leading to reduction in power consumption of the shift register.

Claims

1. A shift register comprising:

a first line;

a second line;

a third line;

a fourth line;

a first stage;

a second stage;

a third stage; and

a fourth stage,

wherein the first line is configured to supply a first clock signal during a first period and a first constant potential during a second period,

wherein the second line is configured to supply a second clock signal that is an inverted clock signal of the first clock signal during the first period and a second constant potential during the second period,

wherein the third line is configured to supply a third clock signal during the second period and a third constant potential during the first period,

wherein the fourth line is configured to supply a fourth clock signal that is an inverted clock signal of the third clock signal during the second period and a fourth constant potential during the first period,

wherein the first stage is electrically connected to the first line such that the first clock signal and the first constant potential are input to the first stage,

wherein the second clock signal and the second constant potential are not input to the first stage,

wherein an output terminal of the first stage is electrically connected to an input terminal of the second stage,

wherein the second stage is electrically connected to the second line such that the second clock signal and the second constant potential are input to the second stage,

wherein the first clock signal and the first constant potential are not input to the second stage,

wherein an output terminal of the second stage is operationally connected to an input terminal of the third stage,

wherein the third stage is electrically connected to the third line such that the third clock signal and the third constant potential are input to the third stage,

wherein the fourth clock signal and the fourth constant potential are not input to the third stage,

wherein an output terminal of the third stage is electrically connected to an input terminal of the fourth stage,

wherein the fourth stage is electrically connected to the fourth line such that the fourth clock signal and the fourth constant potential are input to the fourth stage, and

wherein the third clock signal and the third constant potential are not input to the fourth stage.

2. The shift register according to claim 1, wherein the first stage comprises a transistor including an oxide semiconductor film.

3. A display device comprising the shift register according to claim 1.

4. The shift register according to claim 1,

wherein each of the first stage, the second stage, the third stage and the fourth stage comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and sixth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein a gate of the third transistor is electrically connected to a gate of the second transistor,

wherein a gate of the fourth transistor is electrically connected to the one of the source and the drain of the first transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the fifth transistor is electrically connected to the one of the source and the drain of the third transistor,

wherein a gate of the sixth transistor is electrically connected to the gate of the fourth transistor, and

wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor.

5. The shift register according to claim 1,

wherein each of the first stage, the second stage, the third stage and the fourth stage comprises a first transistor, a second transistor, a third transistor and a fourth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor, and

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor.

6. A shift register comprising:

a first line;

a second line;

a third line;

a fourth line;

a first stage;

a second stage;

a third stage;

a fourth stage;

a fifth stage; and

a sixth stage,

wherein the first line is configured to supply a first clock signal during a first period and a first constant potential during a second period,

wherein the second line is configured to supply a second clock signal that is an inverted clock signal of the first clock signal during the first period and a second constant potential during the second period,

wherein the third line is configured to supply a third clock signal during the second period and a third constant potential during the first period,

wherein the fourth line is configured to supply a fourth clock signal that is an inverted clock signal of the third clock signal during the second period and a fourth constant potential during the first period,

wherein the first stage is electrically connected to the first line such that the first clock signal and the first constant potential are input to the first stage,

wherein the second clock signal and the second constant potential are not input to the first stage,

wherein an output terminal of the first stage is electrically connected to an input terminal of the second stage,

wherein the second stage is electrically connected to the second line such that the second clock signal and the second constant potential are input to the second stage,

wherein the first clock signal and the first constant potential are not input to the second stage,

wherein an output terminal of the second stage is electrically connected to an input terminal of the third stage,

wherein the third stage is electrically connected to the first line such that the first clock signal and the first constant potential are input to the third stage,

wherein the second clock signal and the second constant potential are not input to the third stage,

wherein an output terminal of the third stage is electrically connected to an input terminal of the fourth stage,

wherein the fourth stage is electrically connected to the second line such that the second clock signal and the second constant potential are input to the fourth stage,

wherein the first clock signal and the first constant potential are not input to the fourth stage,

wherein an output terminal of the fourth stage is electrically connected to an input terminal of the fifth stage,

wherein the fifth stage is electrically connected to the third line such that the third clock signal and the third constant potential are input to the fifth stage,

wherein the fourth clock signal and the fourth constant potential are not input to the fifth stage,

wherein an output terminal of the fifth stage is electrically connected to an input terminal of the sixth stage,

wherein the sixth stage is electrically connected to the fourth line such that the fourth clock signal and the fourth constant potential are input to the sixth stage

wherein the third clock signal and the third constant potential are not input to the sixth stage.

7. The shift register according to claim 6, wherein the first stage comprises a transistor including an oxide semiconductor film.

8. A display device comprising the shift register according to claim 6.

9. The shift register according to claim 6,

wherein each of the first stage, the second stage, the third stage, the fourth stage, the fifth stage and the sixth stage comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and sixth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein a gate of the third transistor is electrically connected to a gate of the second transistor,

wherein a gate of the fourth transistor is electrically connected to the one of the source and the drain of the first transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the fifth transistor is electrically connected to the one of the source and the drain of the third transistor,

wherein a gate of the sixth transistor is electrically connected to the gate of the fourth transistor, and

wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor.

10. The shift register according to claim 6,

wherein each of the first stage, the second stage, the third stage, the fourth stage, the fifth stage and the sixth stage comprises a first transistor, a second transistor, a third transistor and a fourth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor, and

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor.