Method and apparatus for automated validation of semiconductor process recipes

• US 8,527,081 B2
• Filed: 03/10/2011
• Issued: 09/03/2013
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Hardy, Charles, Lindley, Roger Alan
• Primary Examiner(s): PATEL, RAMESH B
• Application Number:
  US13/044,747
• Publication Number:
  US 20120053719A1
• Time in Patent Office: 908 Days
• Field of Search: 700103-106, 700/117, 700/121
• US Class Current: 700/104
• CPC Class Codes: G06N 5/025 Extracting rules from data

Abstract

Methods and apparatus for automated validation of semiconductor process steps are provided herein. In some examples, a method for validating a semiconductor process recipe includes: selecting a rule set describing an operating window for a semiconductor process tool; checking parameter values defined by steps in the semiconductor process recipe against limit-checking rules of the rule set to produce first results; determining step types from the steps in the semiconductor process recipe using step definition rules of the rule set to produce second results; checking transitions between the step types against step transition rules of the rule set to produce third results; and generating, using the computer, validation data for use of the semiconductor process recipe with the semiconductor process tool based on the first, the second, and the third results.

Claims

1. A computer-implemented method of validating a semiconductor process recipe, comprising:

selecting a rule set describing an operating window for a semiconductor process tool;

checking parameter values defined by steps in the semiconductor process recipe against limit-checking rules of the rule set to produce first results;

determining step types from the steps in the semiconductor process recipe using step definition rules of the rule set to produce second results;

checking transitions between the step types against step transition rules of the rule set to produce third results; and

generating, using the computer, validation data for use of the semiconductor process recipe with the semiconductor process tool based on the first, the second, and the third results.

2. The method of claim 1, wherein the step of selecting comprises:

obtaining configuration data for the semiconductor process tool; and

selecting the rule set from a plurality of rule sets based on the configuration data.

3. The method of claim 1, wherein the limit-checking rules define constraints for variable parameters of the semiconductor process tool.

4. The method of claim 1, wherein the step definition rules define a set of requirements for each of the step types.

5. The method of claim 1, wherein the step transition rules define allowed and required transitions between step types.

6. The method of claim 1, wherein the validation data includes at least one error indicator describing violation of at least one rule of the rule set.

7. The method of claim 6, wherein the at least one error indicator further describes at least one modification of the semiconductor process recipe to obviate the violation.

8. The method of claim 6, further comprising:

modifying the semiconductor process recipe using the computer to obviate the violation described by the at least one error indicator.

9. The method of claim 8, wherein the step of modifying comprises:

inserting new steps among the steps of the semiconductor process recipe.

10. The method of claim 1, further comprising:

displaying the validation data on a display coupled to the computer using a graphical user interface (GUI).

11. An apparatus for validating a semiconductor process recipe, comprising:

a memory configured to store recipe checker software and a plurality of rule sets describing operating windows for semiconductor process tools; and

a processor, coupled to the memory, configured to execute the recipe checker software to;

select a rule set describing from the plurality of rule sets for a semiconductor process tool;

check parameter values defined by steps in the semiconductor process recipe against limit-checking rules of the rule set to produce first results;

determine step types from the steps in the semiconductor process recipe using step definition rules of the rule set to produce second results;

check transitions between the step types against step transition rules of the rule set to produce third results; and

generate validation data for use of the semiconductor process recipe with the semiconductor process tool based on the first, the second, and the third results.

12. The apparatus of claim 11, wherein the memory is configured to store configuration data for each of the semiconductor process tools, and wherein the processor is configured to select the rule set from the plurality of rule sets based on the configuration data for the semiconductor process tool.

13. The apparatus of claim 11, wherein the limit-checking rules define constraints for variable parameters of the semiconductor process tool, wherein the step definition rules define a set of requirements for each of the step types, and wherein the step transition rules define allowed and required transitions between step types.

14. The apparatus of claim 11, wherein the validation data includes at least one error indicator describing violation of at least one rule of the rule set.

15. The apparatus of claim 14, wherein the processor is further configured to:

modify the semiconductor process recipe using the computer to obviate the violation described by the at least one error indicator.

16. The apparatus of claim 11, further comprising:

a display, coupled to the processor, configured to display the validation data using a graphical user interface (GUI).

17. A non-transitory computer readable medium having instructions stored thereon that when executed by a processor cause the processor to perform a method of validating a semiconductor process recipe, comprising:

selecting a rule set describing an operating window for a semiconductor process tool;

checking parameter values defined by steps in the semiconductor process recipe against limit-checking rules of the rule set to produce first results;

determining step types from the steps in the semiconductor process recipe using step definition rules of the rule set to produce second results;

checking transitions between the step types against step transition rules of the rule set to produce third results; and

generating, using the computer, validation data for use of the semiconductor process recipe with the semiconductor process tool based on the first, the second, and the third results.

18. The non-transitory computer readable medium of claim 17, wherein the limit-checking rules define constraints for variable parameters of the semiconductor process tool, wherein the step definition rules define a set of requirements for each of the step types, and wherein the step transition rules define allowed and required transitions between step types.

19. The non-transitory computer readable medium of claim 17, wherein the validation data includes at least one error indicator describing violation of at least one rule of the rule set, and wherein the at least one error indicator further describes at least one modification of the semiconductor process recipe to obviate the violation.

20. The non-transitory computer readable medium of claim 17, wherein the validation data includes at least one error indicator describing violation of at least one rule of the rule set, and wherein the method further comprises:

modifying the semiconductor process recipe using the computer to obviate the violation described by the at least one error indicator.