System and method for processing digital data

• US 8,527,683 B2
• Filed: 02/17/2010
• Issued: 09/03/2013
• Est. Priority Date: 02/18/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Cauchy, Xavier, Philippe, Anthony, Faugeras, Isabelle, Siron, Didier
• Primary Examiner(s): KNOLL, CLIFFORD H
• Application Number:
  US12/707,451
• Publication Number:
  US 20100211712A1
• Time in Patent Office: 1,294 Days
• Field of Search: 710/110, 713/324, 713/320, 709208-211, 711/100, 345/506
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0038 System on Chip
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Claims

1. A system-on-chip (SoC) comprising:

a set of slave processing units comprising programmable slave processing units and non-programmable hardware slave processing units configured to execute elementary video processing functions respectively on a plurality of parallel video input data streams to generate a combined video data stream;

a data transfer SoC network;

an interconnection module configured to communicate with said data transfer SoC network and to transfer data between said set of slave processing units and said data transfer SoC network; and

a controller configured to control the data transfer.

2. The SoC according to claim 1 further comprising a shared memory associated with said programmable slave processing units.

3. The SoC according to claim 2 wherein said shared memory comprises a memory internal to said programmable slave processing units.

4. The SoC according to claim 1 wherein said interconnection module disables slave processing units not in demand.

5. The SoC according to claim 4 wherein said interconnection module inserts into a signal transmitted to one of said set of slave processing units an active flag for a transaction in progress, and disables the slave processing unit if there is no active flag in the transmitted signal.

6. The SoC according to claim 1 wherein said set of slave processing units is organized in groups having stages with non-simultaneous action;

and further comprising a multiplexer for multiplexing the groups of slave processing units.

7. The SoC according to claim 6 wherein said interconnection module inserts into a signal transmitted to each slave processing unit a configuration signal of the respective group.

8. The SoC according to claim 1 further comprising a plurality of parallel sets of slave processing units, each group associated with a local memory and with a local interconnection module.

9. The SoC according to claim 1 wherein said interconnection module transfers video data.

10. A system for processing digital data comprising:

a set of slave processing units comprising programmable slave processing units and non-programmable hardware slave processing units and configured to execute elementary video processing functions respectively on a plurality of parallel video input data streams to generate a combined video data stream;

a data transfer network;

an interconnection module configured to communicate with said data transfer network and to transfer video data between said set of slave processing units and said data transfer network; and

a controller configured to control the data transfer.

11. The system according to claim 10 further comprising a shared memory associated with said programmable slave processing units.

12. The system according to claim 10 wherein said interconnection module disables slave processing units not in demand.

13. The system according to claim 12 wherein said interconnection module inserts into a signal transmitted to one of said set of slave processing units an active flag for a transaction in progress, and disables the slave processing unit if there is no active flag in the transmitted signal.

14. The system according to claim 10 wherein said set of slave processing units is organized in groups having stages with non-simultaneous action;

and further comprising a multiplexer for multiplexing the groups of slave processing units.

15. A satellite television signal decoder for processing digital data comprising:

a set of slave processing units comprising programmable slave processing units and non-programmable hardware slave processing units and configured to execute elementary video processing functions respectively on a plurality of parallel video input data streams to generate a combined video data stream;

a data transfer network;

an interconnection module configured to communicate with said data transfer network and to transfer video data between said set of slave processing units and said data transfer network; and

a controller configured to control the data transfer.

16. The satellite television signal decoder according to claim 15 further comprising a shared memory associated with said programmable slave processing units.

17. The satellite television signal decoder according to claim 15 wherein said interconnection module disables slave processing units not in demand.

18. The satellite television signal decoder according to claim 15 wherein said interconnection module inserts into a signal transmitted to one of said slave processing units an active flag for a transaction in progress, and disables the slave processing unit if there is no active flag in the transmitted signal.

19. The satellite television signal decoder according to claim 15 wherein said set of slave processing units is organized in groups having stages with non-simultaneous action;

and further comprising a multiplexer for multiplexing the groups of slave processing units.

20. The satellite television signal decoder according to claim 19 wherein said interconnection module inserts into a signal transmitted to each slave processing unit a configuration signal of the respective group.

21. The satellite television signal decoder according to claim 15 wherein said set of slave processing units, said data transfer network, said interconnection module, and said controller are on a System-on-Chip (SoC).

22. A television set processing digital data comprising:

a set of slave processing units comprising programmable slave processing units and non-programmable hardware slave processing units and configured to execute elementary video processing functions respectively on a plurality of parallel video input data streams to generate a combined video data stream;

a data transfer network;

an interconnection module configured to communicate with said data transfer network and to transfer video data between said set of slave processing units and said data transfer network; and

a controller configured to control the data transfer.

23. The television set according to claim 22 further comprising a shared memory associated with said programmable slave processing units.

24. The television set according to claim 22 wherein said interconnection module disables slave processing units not in demand.

25. The television set according to claim 22 wherein said interconnection module inserts into a signal transmitted to one of said set of slave processing units an active flag for a transaction in progress, and disables the slave processing unit if there is no active flag in the transmitted signal.

26. The television set according to claim 22 wherein said set of slave processing units is organized in groups having stages with non-simultaneous action;

and further comprising a multiplexer for multiplexing the groups of slave processing units.

27. The television set according to claim 26 wherein said interconnection module inserts into a signal transmitted to each slave processing unit a configuration signal of the respective group.

28. The television set according to claim 22 wherein said set of slave processing units, said data transfer network, said interconnection module, and said controller are on a System-on-Chip (SoC).

29. A method of making a system for processing digital data on a system-on-chip (SoC), the method comprising:

providing a set of slave processing units for executing elementary video processing functions and comprising programmable slave processing units and non-programmable hardware slave processing units, the elementary video processing functions being processed respectively on a plurality of parallel video input data streams to generate a combined video data stream;

coupling an interconnection module to communicate with a data transfer SoC network and to transfer data between the set of slave processing units and the data transfer SoC network; and

coupling a controller to the interconnection module to control the data transfer.

30. The method according to claim 29 further comprising coupling a shared memory with the set of slave processing units and being associated with the programmable slave processing units.

31. The method according to claim 29 further comprising configuring the interconnection module to disable slave processing units not in demand.

32. The method according to claim 31 further comprising configuring the interconnection module to insert into a signal transmitted to one of the set of slave processing units an active flag for a transaction in progress, and to disable the slave processing unit if there is no active flag in the transmitted signal.

33. The method according to claim 29 further comprising:

organizing the set of slave processing units in groups having stages with non-simultaneous action; and

coupling a multiplexer for multiplexing the groups of slave processing units.