Data storage in analog memory cell arrays having erase failures

• US 8,527,819 B2
• Filed: 10/12/2008
• Issued: 09/03/2013
• Est. Priority Date: 10/19/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Shalvi, Ofir, Winter, Shai, Sommer, Naftali, Sokolov, Dotan
• Primary Examiner(s): LOHN, JOSHUA A
• Application Number:
  US12/677,114
• Publication Number:
  US 20100199150A1
• Time in Patent Office: 1,787 Days
• Field of Search: 714/710, 714/711
• US Class Current: 714/710
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/345 Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A method for data storage includes performing an erasure operation on a group of analog memory cells (32). One or more of the memory cells in the group, which failed the erasure operation, are identified as erase-failed cells. A storage configuration that is used for programming the analog memory cells in the group is modified responsively to the identified erase-failed cells. Data is stored in the group of the analog memory cells using the modified storage configuration.

Claims

1. A method for data storage, comprising:

performing an erasure operation on a group of analog memory cells;

identifying as erase-failed cells one or more of the memory cells in the group that failed the erasure operation;

modifying, responsively to the identified erase-failed cells, a storage configuration that is used for programming the analog memory cells in the group; and

storing data within the group of the analog memory cells containing the identified erase-failed cells using the modified storage configuration.

2. The method according to claim 1, wherein storing the data comprises storing a portion of the data in at least one of the erase-failed cells.

3. The method according to claim 1, wherein identifying the erase-failed cells comprises identifying a distribution of locations of the erase-failed cells across the group of the memory cells, and wherein modifying the storage configuration comprises setting the storage configuration responsively to the identified distribution of the locations.

4. The method according to claim 3, wherein the analog memory cells in the group are arranged in an array having multiple cell sub-groups, such that the cells in each of the sub-groups are programmed simultaneously, and wherein identifying the distribution of the locations comprises identifying a worst-performing sub-group containing a maximum number of the erase-failed cells.

5. The method according to claim 4, wherein identifying the worst-performing sub-group comprises applying a sequence of iterations to the multiple sub-groups, such that each iteration retains only a subset of the sub-groups that were retained by a preceding iteration in the sequence by selecting the subgroups having a count of the erase-failed cells that is above a predefined threshold.

6. The method according to claim 5, wherein the analog memory cells are arranged in multiple rows, wherein each sub-group comprises cells that are located in a respective row, and wherein retaining the subset of the sub-groups comprises biasing the rows corresponding to the sub-groups in the subset with a first bias voltage and biasing the rows corresponding to the sub-groups other than the sub-groups in the subset using a second bias voltage that is different from the first bias voltage.

7. The method according to claim 5, wherein applying the sequence of the iterations comprises predefining a maximum permitted number of the iterations, and terminating the sequence upon reaching the maximum permitted number of the iterations.

8. The method according to claim 3 wherein the memory cells are comprised of a NAND Flash device wherein the cells are arranged in multiple NAND strings and wherein the total number of erase-failed cells is approximated by counting the number of NAND strings having at least one erase-failed cell.

9. The method according to claim 1, wherein the analog memory cells are arranged in multiple columns, and wherein modifying the storage configuration comprises setting the storage configuration responsively to a count of the columns containing at least one of the erase-failed cells.

10. The method according to claim 1, wherein identifying the erase-failed cells is performed in response to receiving a notification of a failure of the erasure operation.

11. The method according to claim 1, wherein modifying the storage configuration comprises modifying an Error Correction Code (ECC) that encodes the data in the group of the memory cells.

12. The method according to claim 1, wherein modifying the storage configuration comprises modifying a storage capacity of at least some of the memory cells in the group.

13. The method according to claim 1, wherein modifying the storage configuration comprises modifying a parameter of an iterative Program and Verify (P&

V) process that is used for storing the data in the group of the memory cells.

14. The method according to claim 1, wherein modifying the storage configuration comprises setting the storage configuration responsively to a count of programming and erasure cycles applied to the group of the memory cells.

15. The method according to claim 1, wherein identifying the erase-failed cells comprises identifying locations of the erase-failed cells in the group of the memory cells and storing the identified locations, and comprising reading the memory cells in the group and reconstructing the data responsively to the stored locations of the erase-failed cells.

16. The method according to claim 15, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), and wherein reconstructing the data comprises decoding the ECC using an ECC decoding process that accepts erasure indications, and identifying the locations of the erase-failed cells as erasure indications to the ECC decoding process.

17. The method according to claim 15, wherein storing the data and reading the memory cells comprise skipping the identified locations of the erase-failed cells.

18. An apparatus for data storage, comprising:

an interface, which is operative to communicate with a memory device that includes a plurality of analog memory cells; and

circuitry, which is coupled to perform an erasure operation on a group of the analog memory cells, to identify as erase-failed cells one or more of the memory cells in the group that failed the erasure operation, to modify, responsively to the identified erase-failed cells, a storage configuration that is used for programming the analog memory cells in the group, and to store data within the group of the analog memory cells containing the identified erase-failed cells using the modified storage configuration.

19. The apparatus according to claim 18, wherein the circuitry is coupled to store a portion of the data in at least one of the erase-failed cells.

20. The apparatus according to claim 18, wherein the circuitry is coupled to identify a distribution of locations of the erase-failed cells across the group of the memory cells, and to modify the storage configuration responsively to the identified distribution of the locations.

21. The apparatus according to claim 20, wherein the analog memory cells in the group are arranged in an array having multiple cell sub-groups, such that the cells in each of the sub-groups are programmed simultaneously, and wherein the circuitry is coupled to identify a worst-performing sub-group containing a maximum number of the erase-failed cells.

22. The apparatus according to claim 21, wherein the circuitry is coupled to identify the worst-performing sub-group by applying a sequence of iterations to the multiple sub-groups, such that each iteration retains only a subset of the sub-groups that were retained by a preceding iteration in the sequence by selecting the subgroups having a count of the erase-failed cells that is above a predefined threshold.

23. The apparatus according to claim 22, wherein the analog memory cells are arranged in multiple rows, wherein each sub-group comprises cells that are located in a respective row, and wherein the circuitry is coupled to retain the subset of the sub-groups by biasing the rows corresponding to the sub-groups in the subset with a first bias voltage and biasing the rows corresponding to the sub-groups other than the sub-groups in the subset using a second bias voltage that is different from the first bias voltage.

24. The apparatus according to claim 22, wherein the circuitry is coupled to predefine a maximum permitted number of the iterations, and to terminate the sequence upon reaching the maximum permitted number of the iterations.

25. The apparatus according to claim 20, wherein the memory device comprises a NAND Flash device, in which the cells are arranged in multiple NAND strings and wherein the total number of erase-failed cells is approximated by counting the number of NAND strings having at least one erase-failed cell.

26. The apparatus according to claim 18, wherein the analog memory cells are arranged in multiple columns, and wherein the circuitry is coupled to modify the storage configuration responsively to a count of the columns containing at least one of the erase-failed cells.

27. The apparatus according to claim 18, wherein the circuitry is coupled to identify the erase-failed cells responsively to receiving a notification of a failure of the erasure operation.

28. The apparatus according to claim 18, wherein the circuitry is coupled to modify the storage configuration by modifying an Error Correction Code (ECC) that encodes the data in the group of the memory cells.

29. The apparatus according to claim 18, wherein the circuitry is coupled to modify the storage configuration by modifying a storage capacity of at least some of the memory cells in the group.

30. The apparatus according to claim 18, wherein the circuitry is coupled to modify the storage configuration by modifying a parameter of an iterative Program and Verify (P&

V) process that is used for storing the data in the group of the memory cells.

31. The apparatus according to claim 18, wherein the circuitry is coupled to modify the storage configuration responsively to a count of programming and erasure cycles applied to the group of the memory cells.

32. The apparatus according to claim 18, wherein the circuitry is coupled to identify locations of the erase-failed cells in the group of the memory cells and storing the identified locations, to read the memory cells in the group and to reconstruct the data responsively to the stored locations of the erase-failed cells.

33. The apparatus according to claim 32, wherein the circuitry is coupled to encode the stored data with an Error Correction Code (ECC), to reconstruct the data by decoding the ECC using an ECC decoding process that accepts erasure indications, and to identify the locations of the erase-failed cells as erasure indications to the ECC decoding process.

34. The apparatus according to claim 32, wherein the circuitry is coupled to skip the identified locations of the erase-failed cells when storing the data and reading the memory cells.

35. The apparatus according to claim 18, wherein the circuitry comprises:

a Read/Write (R/W) unit, which is packaged in the memory device and is coupled to identify the erase-failed cells and to report information regarding the identified erase-failed cells over the interface; and

a processor, which is external to the memory device and is coupled to modify the storage configuration responsively to the information reported by the R/W unit.

36. The apparatus according to claim 18, wherein the circuitry comprises a processor that is external to the memory device.

37. Apparatus for data storage, comprising:

a memory device, which comprises a plurality of analog memory cells; and

a processor, which is coupled to perform an erasure operation on a group of the analog memory cells, to identify as erase-failed cells one or more of the memory cells in the group that failed the erasure operation, to modify, responsively to the identified erase-failed cells, a storage configuration that is used for programming the analog memory cells, and to store data within the group of the analog memory cells containing the identified erase-failed cells using the modified storage configuration.

38. A memory device, comprising:

a plurality of analog memory cells; and

Read/Write (R/W) circuitry, which is coupled to perform an erasure operation on a group of the analog memory cells, to identify as erase-failed one or more of the memory cells in the group that failed the erasure operation, and to report information regarding the identified erase-failed cells to a controller external to the memory device, so as to enable the controller to store data within the group of the analog memory cells containing the identified erase-failed cells.