Apparatus, system, and method for using multi-level cell solid-state storage as reduced-level cell solid-state storage

• US 8,527,841 B2
• Filed: 09/11/2012
• Issued: 09/03/2013
• Est. Priority Date: 03/13/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Wood, Robert, Hyun, Jea Woong
• Primary Examiner(s): Ton, David
• Application Number:
  US13/609,527
• Publication Number:
  US 20130003457A1
• Time in Patent Office: 357 Days
• Field of Search: 714/721, 714/769, 714/773, 365/185.03, 365/185.28
• US Class Current: 714/773
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A controller is used for an electronic memory device which has multi-level cell (MLC) memory elements. The individual MLC memory elements are capable of storing at least two bits. The controller includes a physical interface to couple the controller to the electronic memory device. The controller also includes a processing unit coupled to the physical interface. The processing unit operates the electronic memory device using a restricted number of programming states for a single data bit. The restricted number of programming states includes first and second states used to represent a most significant bit (MSB) of the at least two bits of data of the designated programming states.

Claims

1. A method for storing data in an electronic memory device, the method comprising:

receiving a write command to write data to an electronic memory device having multi-level cell (MLC) memory elements, wherein the individual MLC memory elements are programmable to programming states in a MLC mode, wherein each programming state in the MLC mode is representative of at least two bits of data; and

programming at least one of the MLC memory elements to one of a plurality of programming states in a reduced-level cell (RLC) mode, wherein the programming states in the RLC mode exclude at least one of the programming states in the MLC mode, and the programming states in the RLC mode comprise first and second states used to represent a most significant bit (MSB) of the at least two bits of data of the programming states in the MLC mode.

2. The method of claim 1, wherein programming the MLC memory element to one of the programming states in the RLC mode further comprises programming the MLC memory element to represent a page bit within a page tuple, wherein the page bit corresponds to the MSB of a bit pair corresponding to one of the programming states in the MLC mode.

3. The method of claim 2, wherein the first state represents a first binary value of the MSB, and the second state represents a second binary value of the MSB.

4. The method of claim 2, further comprising reading the MLC memory element by determining the programming state in the RLC mode to which the MLC memory element is programmed.

5. The method of claim 4, wherein determining the programming state in the RLC mode to which the MLC memory element is programmed further comprises performing a single read operation to determine whether the MLC memory element is programmed to the first state or the second state of the programming states in the RLC mode.

6. The method of claim 1, wherein the programming states in the RLC mode comprise only a subset of the programming states to which the MLC memory element is programmable in the MLC mode.

7. The method of claim 1, wherein the RLC mode comprises a single-level cell (SLC) mode, wherein each programming state in the SLC mode is representative of a single bit of data, and the method further comprises dynamically switching between the MLC mode and the SLC mode in response to a trigger event by way of not addressing one or more pages comprising certain bits of the MLC memory elements.

8. The method of claim 1, further comprising dynamically switching between two SLC modes in response to a trigger event, wherein a first SLC mode uses the MSB states to store the data, and a second SLC mode uses least significant bit (LSB) states to store the data.

9. The method of claim 1, further comprising:

defining the programming states in the RLC to include the first and second states used to represent the MSB of the at least two bits of the programming states in the MLC mode; and

restricting programming access during operation of the electronic memory device in the RLC mode to only the programming states defined in the RLC mode.

10. The method of claim 1, wherein the RLC mode comprises a single-level cell (SLC) mode in which each programming state is representative of one bit of data, and each programming state in the MLC mode is representative of three bits of data, and the method further comprises dynamically switching between the MLC mode and the SLC mode in response to a trigger event.

11. The method of claim 1, wherein the MLC mode comprises a first MLC mode in which each programming state is representative of at least three bits of data, and the RLC mode comprises a second MLC mode in which each programming state is representative of two bits of data, and the method further comprises dynamically switching between the first MLC mode and the second MLC mode in response to a trigger event.

12. The method of claim 1, wherein the first state comprises an erase state, and the second state comprises a lower state of a pair of adjacent states of the programming states in the MLC mode, wherein the pair of adjacent states of the programming states in the MLC mode represent bit values with a common MSB value.

13. A system, comprising:

an electronic memory device having multi-level cell (MLC) memory elements, wherein the individual MLC memory elements are programmable to 2X programming states in a MLC mode, wherein each programming state is representative of X bits of data, where X>

1; and

a processor coupled to the electronic memory device, wherein the processor is configured to receive a write command to write data to the electronic memory device and to program at least one of the MLC memory elements to one of a plurality of programming states in a reduced-level cell (RLC) mode to represent Y bits of the data, where Y<

X, wherein the programming states in the RLC mode exclude at least one of the programming states in the MLC mode, and the restricted programming states in the RLC mode comprise first and second states used to represent a most significant bit (MSB) of the programming states in the MLC mode.

14. The system of claim 13, wherein the processor is further configured to program the MLC memory element to represent a page bit within a page tuple, wherein the page bit corresponds to the MSB of a bit pair corresponding to one of the programming states in the MLC mode.

15. The system of claim 14, wherein the processor is further configured to read the MLC memory element by determining the programming state in the RLC mode to which the MLC memory element is programmed.

16. The system of claim 15, wherein the processor is further configured to perform a single read operation to determine whether the MLC memory element is programmed to the first state or the second state of the programming states in the RLC mode.

17. The system of claim 13, wherein the processor is further configured to dynamically switch between the RLC mode and the MLC mode in response to a trigger event by way of not addressing one or more pages comprising certain bits of the MLC memory elements.

18. The system of claim 13, wherein the processor is further configured to dynamically switch between two SLC modes, wherein a first SLC mode uses most significant bit (MSB) states to store the data, and a second SLC mode uses least significant bit (LSB) states to store the data.

19. An electronic memory device comprising:

a physical interface to couple the electronic memory device to a controller; and

N-level cell (NLC) memory elements, wherein the individual NLC memory elements are capable of storing at least two data bits in a NLC mode, wherein the individual NLC memory elements are configured to operate in a reduced-level cell (RLC) mode using a number of programming states in the RLC mode, wherein the number of programming states in the RLC mode comprise a lower state of a pair of adjacent states of the programming states in NLC mode, wherein the pair of adjacent states of the programming states in the NLC mode represent bit values with a common MSB value.

20. The controller of claim 19, wherein the programming states in the RLC mode comprise only a subset of the designated programming states to which the NLC memory element is programmable in the NLC mode.