Production process for semiconductor device

• US 8,530,256 B2
• Filed: 03/09/2012
• Issued: 09/10/2013
• Est. Priority Date: 03/11/2011
• Status: Active Grant

• Current Assignee: Stanley Electric Company Limited
• Original Assignee: Stanley Electric Company Limited
• Inventors: Shibata, Yasuyuki, Liang, Ji-Hao, Chinone, Takako
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US13/416,635
• Publication Number:
  US 20120231608A1
• Time in Patent Office: 550 Days
• Field of Search: 438/46, 438/456, 438/458, 438/928, 438/960, 438/977, 257/E33.006, 257/E33.025, 257/E21.087, 257/E21.119
• US Class Current: 438/46
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate

Abstract

(a) Forming on a growth substrate a void-containing layer that is made of a group III nitride compound semiconductor and contains voids. (b) Forming on the void-containing layer an n-type layer that is made of an n-type group III nitride compound semiconductor and serves to close the voids. (c) Forming on the n-type layer an active layer made of a group III nitride compound semiconductor. (d) Forming on the active layer a p-type layer made of a p-type group III nitride compound semiconductor. (e) Bonding a support substrate above the p-type layer. (f) Peeling off the growth substrate at the boundary where the void are produced. (g) Planarizing the n-type layer. Step (b) comprises (b1) forming part of the n-type layer under conditions where horizontal growth is relatively weak and (b2) forming the remaining part of the n-type layer under conditions where horizontal growth is relatively strong.

Claims

1. A semiconductor device production process comprising:

(a) forming on a growth substrate a void-containing layer that is made of a group III nitride compound semiconductor and contains voids,

(b) forming on the void-containing layer an n-type layer that is made of an n-type group III nitride compound semiconductor and serves to close the voids,

(c) forming on the n-type layer an active layer made of a group III nitride compound semiconductor,

(d) forming on the active layer a p-type layer made of a p-type group III nitride compound semiconductor,

(e) bonding a support substrate above the p-type layer,

(f) peeling off the growth substrate at the boundary where the void are produced, and

(g) planarizing the n-type layer, wherein

(b) above comprises

(b1) forming part of the n-type layer under conditions where horizontal growth is relatively weak, and

(b2) forming the remaining part of the n-type layer under conditions where horizontal growth is relatively strong.

2. A semiconductor device production process as claimed in claim 1 wherein the shift from (b1) to (b2) takes place when the opening ratio of the voids has reached a value in the range of 5% to 40%.

3. A semiconductor device production process as claimed in claim 1 wherein the temperature for forming an n-type layer in (b2) is higher than the temperature for forming an n-type layer in (b1).

4. A semiconductor device production process as claimed in claim 3 wherein in (b1), an n-type layer is formed in the temperature range of 995°

C. to 1,005°

C. while in (b2), an n-type layer is formed in the temperature range of 1,010°

C. to 1,030°

C.