Method of making oxide thin film transistor array

• US 8,530,273 B2
• Filed: 09/29/2010
• Issued: 09/10/2013
• Est. Priority Date: 09/29/2010
• Status: Expired due to Fees

• Current Assignee: Guardian Glass LLC (KOCH Industries Incorporated)
• Original Assignee: Guardian Industries Corporation (KOCH Industries Incorporated)
• Inventors: Den Boer, Willem
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US12/923,624
• Publication Number:
  US 20120074399A1
• Time in Patent Office: 1,077 Days
• Field of Search: 438/85, 438/104, 438/149, 438/754, 257/43, 257/E21.533
• US Class Current: 438/104
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Certain example embodiments relate to methods of making oxide thin film transistor arrays (e.g., IGZO, amorphous or polycrystalline ZnO, ZnSnO, InZnO, and/or the like), and devices incorporating the same. Blanket layers of an optional barrier layer, semiconductor, gate insulator, and/or gate metal are disposed on a substrate. These and/or other layers may be deposited on a soda lime or borosilicate substrate via low or room temperature sputtering. These layers may be later patterned and/or further processed in making a TFT array according to certain example embodiments. In certain example embodiments, all or substantially all TFT processing may take place at a low temperature, e.g., at or below 150 degrees C., until a post-annealing activation step, and the post-anneal step may take place at a relatively low temperature (e.g., 200-250 degrees C.).

Claims

1. A method of making a TFT substrate for an electronic device, the method comprising:

sputter depositing an oxide semiconductor layer, directly or indirectly, on a soda-lime based glass substrate;

depositing a gate insulator blanket layer, directly or indirectly, on the oxide semiconductor layer;

depositing a gate metal blanket layer, directly or indirectly, on the gate insulator blanket layer;

applying a mask over one or more portions of the gate metal blanket layer so as to define one or more corresponding masked areas and one or more corresponding unmasked areas;

removing portions of the gate metal blanket layer and portions of the gate insulator blanket layer at or proximate to the one or more unmasked areas;

increasing conductivity of the oxide semiconductor layer at the one or more unmasked areas then patterning the oxide semiconductor layer into a plurality of islands;

disposing a passivation layer across substantially the entire substrate;

patterning the passivation layer so as to define source and drain contact holes;

depositing a layer for source and drain connections; and

wherein all TFT processing steps are performed at or below about 150 degrees C., until a post-annealing activation step is performed at 200-250 degrees C.

2. The method of claim 1, wherein the oxide semiconductor layer comprises indium gallium zinc oxide (IGZO).

3. The method of claim 2, wherein the increasing of the conductivity of the oxide semiconductor layer is accomplished via a plasma treatment.

4. The method of claim 3, wherein the plasma treatment is H or Ar plasma treatment.

5. The method of claim 2, further comprising annealing the substrate with the layers formed thereon following deposition of the source and drain connections.

6. The method of claim 1, further comprising depositing a silicon-inclusive barrier layer on and directly contacting the glass substrate.

7. The method of claim 1, wherein the mask is a photoresist.

8. A method of making an electronic display device, the method comprising:

making a TFT substrate according to the method of claim 1.

9. The method of claim 8, further comprising:

providing a color filter substrate; and

disposing a layer of liquid crystal material between the color filter substrate and the TFT substrate.

10. The method of claim 1, wherein the oxide semiconductor layer is originally deposited as a blanket layer so as to cover a substantial portion of the glass substrate, and wherein said increasing conductivity of the oxide semiconductor layer is performed on the oxide semiconductor blanket layer, and following said increasing conductivity of the oxide semiconductor blanket layer the oxide semiconductor blanket layer is patterned to form at least a plurality of islands.

11. The method of claim 1, wherein following said increasing conductivity of the oxide semiconductor layer, the oxide semiconductor layer is patterned to form at least a plurality of islands.

12. The method of claim 1, wherein said sputter depositing of the oxide semiconductor layer is at approximately room temperature.

13. A method of making a coated article to be used in the production of a TFT substrate for an electronic device, the method comprising:

sputter depositing, at approximately room temperature, an oxide semiconductor layer, directly or indirectly, on a soda-lime based glass substrate;

depositing a gate insulator layer, directly or indirectly, on the oxide semiconductor layer; and

depositing a gate metal layer, directly or indirectly, on the gate insulator layer, wherein;

a mask is applied over one or more portions of the gate metal layer so as to define one or more corresponding masked areas and one or more corresponding unmasked areas,

portions of the gate metal layer and portions of the gate insulator layer are to be removed in areas defined by the mask,

conductivity of the oxide semiconductor layer is increased at one or more unmasked areas,

after increasing conductivity of the oxide semiconductor layer, patterning the oxide semiconductor layer into a plurality of islands;

a passivation layer is disposed across at least a substantial portion of the substrate,

the passivation layer is patterned so as to define source and drain contact holes,

a layer for source and drain connections is deposited; and

wherein all TFT processing steps are performed at or below about 150 degrees C. until a post-annealing activation step is performed at 200-250 degrees C.

14. The method of claim 13, wherein the oxide semiconductor material comprises indium gallium zinc oxide (IGZO).

15. The method of claim 13, further comprising depositing a silicon-inclusive barrier layer on and directly contacting the glass substrate.

16. The method of claim 13, wherein the conductivity of the oxide semiconductor layer is increased via H plasma treatment.

17. The method of claim 13, wherein the conductivity of the oxide semiconductor layer is increased via Ar plasma treatment.