Low power semiconductor transistor structure and method of fabrication thereof

• US 8,530,286 B2
• Filed: 12/17/2010
• Issued: 09/10/2013
• Est. Priority Date: 04/12/2010
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Shifren, Lucian, Ranade, Pushkar, Thompson, Scott E., Sonkusale, Sachin R., Zhang, Weimin
• Primary Examiner(s): Li, Meiya
• Application Number:
  US12/971,884
• Publication Number:
  US 20110248352A1
• Time in Patent Office: 998 Days
• Field of Search: 257/204, 257/337, 257/338, 257/351, 257/368, 257/374, 257/402, 257/406, 257499-501, 257/506, 257/510, 257/E27.046, 257/E27.059, 257/E27.06, 257/E27.062, 257/E27.064, 257/E27.067, 257/E21.002, 257/E21.532, 257/E21.536, 257/E21.54, 257/E21.546, 257/E21.598, 257/E21.602, 257/E21.611, 257/E21.618, 257/E21.625, 257/E21.632, 257/E21.633, 257/E21.639, 438/151, 438/154, 438/166, 438/174, 438/194, 438/196, 438/199, 438/207, 438/217, 438/218, 438/221, 438/275, 438/289, 438/294, 438/424, 438/514, 438/522, 438/530, 438/FOR.187, 438/FOR.216, 438/FOR.227
• US Class Current: 438/151
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV_T compared to conventional bulk CMOS and can allow the threshold voltage V_T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Claims

1. A method for fabricating an integrated circuit having transistor devices defined on a substrate:

forming a first screening layer for a first digital device, the first screening layer being positioned below a first gate of the first digital device, the first screening layer having a first dopant concentration between 1×

10¹⁸ to 1×

10²⁰ atoms/cm³;

forming a second screening layer for a second device type, the second screening layer being positioned below a second gate of the second device type, the second screening layer having a second dopant concentration between 1×

10¹⁸ to 1×

10²⁰ atoms/cm³;

performing an epitaxial deposition to form a common epitaxial layer for the first digital device and the second device type, the common epitaxial layer being positioned above and adjacent to the first screening layer and the second screening layer;

maintaining at least a portion of the common epitaxial layer as a substantially undoped channel region for the first digital device, the substantially undoped channel region of the first digital device having a first dopant concentration less than 5×

10 atoms/cm³; and

performing a shallow trench isolation between the first digital device and the second device type by etching the common epitaxial layer to form a trench and depositing a dielectric within the trench, the shallow trench isolation being performed after forming the common epitaxial layer, wherein the shallow trench isolation extends beyond the first screening layer and the second screening layer.

2. The method of claim 1, wherein forming the first screening layer comprises implanting the first screening layer into the substrate, and wherein forming the second screening layer comprises implanting the second screening layer into the substrate.

3. The method of claim 2, further comprising:

performing low temperature recrystallization annealing after implanting the first screening layer and the second screening layer.

4. The method of claim 3, wherein the low temperature crystallization anneal is performed at a temperature range of 550°

C. to 600°

C.

5. The method of claim 2, further comprising:

performing a high temperature annealing after implanting the first screening layer and the second screening layer;

forming an oxide layer on the substrate after performing the high temperature annealing; and

stripping the oxide layer before performing the epitaxial deposition to form the common epitaxial layer.

6. The method of claim 5, wherein forming the oxide layer on the substrate comprises forming a thin oxide layer on the substrate.

7. The method of claim 1, wherein forming the first screening layer for the first digital device further comprises forming a first P-type screening layer for a first transistor element of the first digital device, and forming a first N-type screening layer for a second transistor element of the first digital device.

8. The method of claim 7, further comprising:

forming a body tap operable to apply a body bias voltage to one or more of the transistor element of the first digital device.

9. The method of claim 1, wherein forming the second screening layer for the second device type further comprises forming a second P-type screening layer for a first transistor element of the second device type, and forming a second N-type screening layer for a second transistor element of the second device type.

10. The method of claim 9, further comprising:

implanting a P-type well for the first transistor element of the second device type;

implanting an N-type well for the second transistor element of the second device type;

implanting a P-type layer over the second P-type screening layer, that wherein the P-type layer operates as a first threshold voltage control layer for the first transistor element of the second device type; and

implanting an N-type layer over the second N-type screening layer, that wherein the N-type layer operates as a second threshold voltage control layer for the second transistor element of the second device type.

11. The method of claim 10, further comprising:

forming a body tap to at least one of the P-type and N-type wells, the body tap being operable to apply a bias voltage to the transistor body.

12. The method of claim 1, further comprising:

performing a diffusion prevention treatment.

13. The method of claim 12, wherein performing the diffusion prevention treatment further comprises implanting at least one of indium and carbon.

14. The method of claim 12, wherein performing the diffusion prevention treatment further comprises forming a semiconductor layer between the screening layer and the common epitaxial layer.

15. The method of claim 14, the semiconductor layer includes carbon.

16. The method of claim 14, wherein forming the semiconductor layer comprises depositing SiGe before forming the common epitaxial layer.

17. The method of claim 1, wherein the second device type is a digital legacy device having post-epitaxial deposition channel implants to provide legacy transistor functionality.

18. The method of claim 1, wherein

the second device type is an analog device.

19. The method of claim 1, further comprising:

forming one of single, double, or triple gate oxidation layers for each device.