Methods and apparatus for measuring analytes using large scale FET arrays
First Claim
1. A method for fabricating a chemFET sensor, the method comprising:
- forming a source and a drain of a first semiconductor type in a substrate of a second semiconductor type;
depositing a gate oxide layer on the substrate between the source and the drain;
forming a floating gate on the gate oxide, the floating gate comprising conductors formed in a plurality of conductor layers and electrically coupled to one another wherein forming the floating gate includes;
depositing a first conductor overlying the gate oxide layer;
depositing a dielectric on the first conductor; and
etching the first conductor and the dielectric together;
forming access lines comprising conductors within at least two of the conductor layers and coupled to the source and the drainforming a passivation layer coupled to the etched first conductor.
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Abstract
Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.
449 Citations
21 Claims
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1. A method for fabricating a chemFET sensor, the method comprising:
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forming a source and a drain of a first semiconductor type in a substrate of a second semiconductor type; depositing a gate oxide layer on the substrate between the source and the drain; forming a floating gate on the gate oxide, the floating gate comprising conductors formed in a plurality of conductor layers and electrically coupled to one another wherein forming the floating gate includes; depositing a first conductor overlying the gate oxide layer; depositing a dielectric on the first conductor; and etching the first conductor and the dielectric together;
forming access lines comprising conductors within at least two of the conductor layers and coupled to the source and the drainforming a passivation layer coupled to the etched first conductor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for fabricating a chemFET sensor, the method comprising:
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forming a source and a drain in a semiconductor substrate; depositing a gate oxide layer on the substrate between the source and the drain; forming a floating gate on the gate oxide layer, the floating gate comprising conductors formed in a plurality of conductor layers and electrically coupled to one another wherein forming the floating gate includes; depositing a first conductor overlying the gate oxide layer; depositing a dielectric overlying the first conductor; etching the first conductor and the dielectric together; removing the etched dielectric; and
forming access lines comprising conductors within at least two of the conductor layers and coupled to the source and the drain; andforming a passivation layer on the etched first conductor. - View Dependent Claims (14, 15)
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16. A method for fabricating a chemFET sensor, the method comprising:
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forming a source and a drain of a first semiconductor type in a substrate of a second semiconductor type; depositing a gate oxide layer on the substrate between the source and the drain; forming a floating gate on the gate oxide, the floating gate comprising conductors formed in a plurality of conductor layers and electrically coupled to one another wherein forming the floating gate includes; forming a lower conductor on the gate oxide; and forming an upper conductor electrically coupled to the lower conductor, wherein forming the upper conductor comprises forming a dielectric on the upper conductor and etching the upper conductor and the dielectric together; forming access lines comprising conductors within at least two of the conductor layers and coupled to the source and the drain; and forming a passivation layer coupled to the etched upper conductor. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification