Interconnect barrier structure and method

• US 8,531,035 B2
• Filed: 08/31/2011
• Issued: 09/10/2013
• Est. Priority Date: 07/01/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chiou, Wen-Chih, Wu, Tsang-Jiuh
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US13/222,639
• Publication Number:
  US 20130001783A1
• Time in Patent Office: 741 Days
• Field of Search: 257/773, 257/774, 438/637, 438/643, 438/667
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/04953 TaN
• CPC Class Codes: H01L 2924/15788 Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device.

Claims

1. A device comprising:

conductive material extending from a first side of a substrate to a second side of the substrate, wherein the conductive material is planar with the second side of the substrate;

a first barrier layer located between the conductive material and the substrate, the first barrier layer comprising a first material;

a second barrier layer located along the first side of the substrate and the conductive material, the second barrier layer comprising a second material different than the first material; and

a third barrier layer located along the second side of the substrate and the conductive material, the third barrier layer comprising a third material different than the first material.

2. The device of claim 1, wherein the second material is the same as the third material.

3. The device of claim 1, wherein the first barrier layer is a composite barrier layer.

4. The device of claim 3, wherein the composite barrier layer further comprises:

a first layer of titanium; and

a second layer of titanium nitride.

5. The device of claim 1, wherein a first step coverage of the first barrier layer is greater than a second step coverage of the second barrier layer.

6. The device of claim 1, further comprising a conductive connector adjacent to the third barrier layer.

7. The device of claim 6, wherein the conductive connector is a copper pillar.

8. The device of claim 7, wherein the conductive connector is a redistribution layer.

9. A device comprising:

a first opening through a substrate, the first opening having a first width, the substrate having a first side and a second side;

a first dielectric layer over the first side of the substrate;

a second opening through the first dielectric layer, the second opening having a second width greater than the first width;

a first barrier layer located along sidewalls of the first opening and the second opening, the first barrier layer comprising a first material;

a conductive material located within the first opening and the second opening; and

a second barrier layer located along the second side of the substrate and in physical contact with the conductive material located within the first opening having the first width, the second barrier layer comprising a second material different from the first material.

10. The device of claim 9, wherein the substrate further comprises a second dielectric layer adjacent the first dielectric layer.

11. The device of claim 9, wherein the first barrier layer is a composite barrier layer.

12. The device of claim 11, wherein the composite barrier layer further comprises:

a layer of titanium; and

a layer of titanium nitride.

13. The device of claim 9, further comprising a conductive connector adjacent to the second barrier layer.

14. The device of claim 13, wherein the conductive connector is a copper pillar.

15. The device of claim 13, wherein the conductive connector is a redistribution layer.

16. The device of claim 9, wherein the substrate comprises silicon.

17. A method of manufacturing a device, the method comprising:

forming an opening in a first side of a substrate, the opening comprising sidewalls;

forming a first barrier layer along the sidewalls of the opening, the first barrier layer comprising a first material, the forming the first barrier layer being performed at least in part by a first process;

filling the opening with a first conductive material;

forming a second barrier layer over the conductive material, wherein the forming the second barrier layer is performed at least in part by a second process different than the first process;

thinning a second side of the substrate to expose the first conductive material within the opening, the thinning planarizing the first conductive material and the substrate; and

forming a third barrier layer in physical contact with the planarized conductive material and over the second side of the substrate, wherein the forming the third barrier layer is performed at least in part by a third process different from the first process.

18. The method of claim 17, wherein the forming the first process is chemical vapor deposition.

19. The method of claim 18, wherein the second process is physical vapor deposition.

20. The method of claim 17, wherein the forming the first barrier layer further comprises:

forming a layer of titanium; and

forming a layer of titanium nitride.