Top layers of metal for high performance IC's

• US 8,531,038 B2
• Filed: 07/27/2007
• Issued: 09/10/2013
• Est. Priority Date: 12/21/1998
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Pham, Long
• Application Number:
  US11/829,110
• Publication Number:
  US 20070262457A1
• Time in Patent Office: 2,237 Days
• Field of Search: 257/778, 257/691, 257/692, 257/758, 257/759, 257/760
• US Class Current: 257/778
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 : Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 428/12542 : More than one such component
• CPC Class Codes: Y10T 428/12993 : Surface feature [e.g., rough, mirror]

Abstract

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Claims

1. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said passivation layer comprises a nitride layer;

a second metallization structure over said passivation layer and on said first and second contact points, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises electroplated copper; and

a first polymer layer between said third and fourth metal layers.

2. The integrated circuit chip of claim 1, wherein said second metallization structure comprises a power interconnect connecting said first contact point to said second contact point.

3. The integrated circuit chip of claim 1, wherein said second metallization structure comprises a ground interconnect connecting said first contact point to said second contact point.

4. The integrated circuit chip of claim 1, wherein said first opening has a width between 0.5 and 3 micrometers.

5. The integrated circuit chip of claim 1 further comprising a second polymer layer on said passivation layer, wherein a third opening in said second polymer layer is over said first contact point, and a fourth opening in said second polymer layer is over said second contact point, wherein said third metal layer is on said second polymer layer.

6. The integrated circuit chip of claim 5, wherein said second polymer layer has a thickness between 2 and 30 micrometers.

7. The integrated circuit chip of claim 5, wherein said second polymer layer comprises polyimide.

8. The integrated circuit chip of claim 1, wherein said nitride layer has a thickness between 0.5 and 2 micrometers.

9. The integrated circuit chip of claim 1, wherein said first polymer layer comprises polyimide.

10. The integrated circuit chip of claim 1, wherein said second metallization structure comprises a signal interconnect connecting said first contact point to said second contact point.

11. The integrated circuit chip of claim 1, wherein said passivation layer further comprises an oxide layer under said nitride layer.

25. The integrated circuit chip of claim 1, wherein said second metal interconnect has a portion spaced apart from said portion of said first metal interconnect, wherein said portion of said first metal interconnect comprises said first contact point, and wherein said portion of said second metal interconnect comprises said second contact point.

12. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a separating layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said separating layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said separating layer comprises a nitride layer having a thickness between 0.5 and 2 micrometers;

a second metallization structure over said passivation layer and on said first and second contact points, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, wherein said first contact point is connected to said second contact point through said second metallization structure, and wherein said second metallization structure comprises electroplated copper; and

a first polymer layer between said third and fourth metal layers.

13. The integrated circuit chip of claim 12, wherein said first opening has a width between 0.5 and 3 micrometers.

14. The integrated circuit chip of claim 12, wherein said second metallization structure comprises a power interconnect connecting said first contact point to said second contact point.

15. The integrated circuit chip of claim 12, wherein said second metallization structure comprises a ground interconnect connecting said first contact point to said second contact point.

16. The integrated circuit chip of claim 12 further comprising a second polymer layer on said separating layer, wherein a third opening in said second polymer layer is over said first contact point, and a fourth opening in said second polymer layer is over said second contact point, wherein said third metal layer is on said second polymer layer.

17. The integrated circuit chip of claim 16, wherein said second polymer layer has a thickness between 2 and 30 micrometers.

18. The integrated circuit chip of claim 16, wherein said second polymer layer comprises polyimide.

19. The integrated circuit chip of claim 12, wherein said first polymer layer comprises polyimide.

26. The integrated circuit chip of claim 12, wherein said second metal interconnect has a portion spaced apart from said portion of said first metal interconnect, wherein said portion of said first metal interconnect comprises said first contact point, and wherein said portion of said second metal interconnect comprises said second contact point.

20. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a topmost sub-micron integrated circuit of said integrated circuit chip;

a second dielectric layer between said first and second metal layers;

a separating layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said separating layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said first opening has a width between 0.5 and 3 micrometers;

a second metallization structure over said separating layer and on said first and second contact points, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises electroplated copper; and

a polymer layer between said third and fourth metal layers.

21. The integrated circuit chip of claim 20, wherein said separating layer comprises a nitride layer.

22. The integrated circuit chip of claim 20, wherein said separating layer comprises a nitride layer having a thickness between 0.5 and 2 micrometers.

23. The integrated circuit chip of claim 20, wherein said separating layer comprises an oxide layer.

24. The integrated circuit chip of claim 20, wherein said separating layer comprises an oxide layer having a thickness between 0.15 and 2 micrometers.

27. The integrated circuit chip of claim 20, wherein said second metal interconnect has a portion spaced apart from said portion of said first metal interconnect, wherein said portion of said first metal interconnect comprises said first contact point, and wherein said portion of said second metal interconnect comprises said second contact point.