Configurable critical path emulator

• US 8,531,225 B1
• Filed: 05/18/2012
• Issued: 09/10/2013
• Est. Priority Date: 05/18/2012
• Status: Active Grant

• Current Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Original Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Inventors: Hussain, Adil
• Primary Examiner(s): LUU, AN T
• Application Number:
  US13/474,717
• Time in Patent Office: 480 Days
• Field of Search: 327261-262, 327269-272, 327276-278
• US Class Current: 327/276
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

The subject matter of this application is embodied in an apparatus that includes a configurable delay circuit comprising a plurality of delay elements, and a lookup table having information for configuring the delay circuit based on one or more conditions. The apparatus also includes a controller to configure the delay circuit according to the information in the lookup table, and a sampling circuit to sample outputs of each of a subset of the delay elements and generate a multi-bit delay signal providing information about an amount of delay caused by the delay elements to an input signal propagating through the configurable delay circuit. Each bit in the multi-bit delay signal indicates whether the input signal has propagated through a corresponding delay element.

Claims

1. An apparatus comprising:

a configurable delay circuit comprising a plurality of delay elements;

a lookup table having information for configuring the delay circuit based on one or more conditions;

a controller to configure the delay circuit according to the information in the lookup table; and

a sampling circuit to sample outputs of each of a subset of the delay elements and generate a multi-bit delay signal providing information about an amount of delay caused by the delay elements to an input signal propagating through the configurable delay circuit, each bit in the multi-bit delay signal indicating whether the input signal has propagated through a corresponding delay element.

2. The apparatus of claim 1 in which the configurable delay circuit emulates at least one critical path in a data processor.

3. The apparatus of claim 1 in which the sampling circuit comprises sampling elements that are associated with the subset of the delay elements, each sampling element corresponding to one of the delay elements in the subset, the multi-bit delay signal being generated based on the outputs of the sampling elements.

4. The apparatus of claim 3, comprising

a power supply to provide power to the configurable delay circuit, and

a voltage regulator to regulate a voltage level provided by the power supply,

in which the controller controls the voltage regulator to regulate the power supply voltage level according to the multi-bit delay signal.

5. The apparatus of claim 4 in which the sampling circuit samples the output of the subset of delay elements at a sampling time point, and the controller controls the voltage regulator to regulate the power supply voltage level such that the input signal propagates through approximately half of the subset of the delay elements at the sampling time point.

6. The apparatus of claim 5 in which the controller controls the voltage regulator to regulate the power supply voltage level such that approximately half of the bits in the multi-bit signal is 1 and half of the bits in the multi-bit signal is 0 at the sampling time point.

7. The apparatus of claim 6 in which the sampling circuit comprises latches to latch the output of the subset of the delay elements, the latches operate according to a clock signal, and the sampling time point corresponds to an edge of the clock signal.

8. The apparatus of claim 1, comprising a power supply to provide power to the configurable delay circuit, in which the controller controls an output voltage level of the power supply according to the multi-bit delay signal provided by the sampling circuit.

9. The apparatus of claim 1, comprising

a data processor;

a power supply to provide power to the data processor and the configurable delay circuit;

a voltage regulator to regulate a voltage level provided by the power supply;

wherein the look-up table also has target voltage values each corresponding to one or more conditions, and

the controller at various time points controls the voltage regulator based on target voltage values obtained from the look-up table, and in between the time points, the controller controls the voltage regulator based on multi-bit delay signals provided by the sampling circuit.

10. The apparatus of claim 1 in which each of the plurality of logic elements comprises at least one of an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate, a multiplexer, an inverter, or a logic circuit comprising at least two logic gates.

11. The apparatus of claim 1 in which the configurable delay circuit comprises multiplexers to select combinations of logic gates, and the lookup table has information for configuring the multiplexers for various conditions.

12. An apparatus comprising:

a data processor;

a configurable delay circuit comprising a plurality of delay elements, different combinations of the delay elements representing different delay paths in the configurable delay circuit;

a sampling circuit to sample outputs of each of a subset of the delay elements and generate multi-bit delay signals providing information about delays caused by the delay elements to input signals propagating through the configurable delay circuit; and

a calibration module to evaluate each of a plurality of combinations of the delay elements based on the multi-bit delay signals and identify one or more combinations of the delay elements for emulating one or more critical paths of the data processor at various conditions.

13. The apparatus of claim 12 in which the sampling circuit comprises sampling elements that are associated with the subset of the delay elements, each sampling element corresponding to one of the delay elements in the subset, the outputs of the sampling elements indicating which delay elements the input signal has propagated through during a sampling period, the delay signal being generated based on the output of the sampling elements.

14. The apparatus of claim 12 in which the calibration module is configured to send input signals to each of a plurality of combinations of the delay elements, gradually reducing a power supply voltage provided to the data processor and the configurable delay circuit, evaluating the outputs of the subset of the delay elements when the data processor fails, and evaluating the outputs of the subset of the delay elements at a power supply voltage level higher, by a safety margin, than the voltage level at which the data processor fails.

15. The apparatus of claim 14 in which the calibration module is configured to identify candidate combinations of the delay elements in which at the power supply voltage level higher, by the safety margin, than the voltage level at which the data processor fails, the input signal has propagated through some, but not all, of the subset of delay elements during a sampling time period.

16. The apparatus of claim 15 in which when there are more than one candidate, the calibration module is configured to identify a candidate that tracks at least one of temperature or frequency better than the other candidates.

17. The apparatus of claim 12 comprising a lookup table to store information for configuring the configurable delay circuit based on one or more conditions, the information being determined based on the evaluation performed by the calibration module.

18. An apparatus comprising:

a data processor;

a configurable delay circuit comprising a plurality of multiplexers and delay elements, different configurations of the multiplexers being associated with different delay paths that comprise different combinations of the delay elements;

a sampling circuit to sample outputs of a subset of the delay elements associated with a delay path and generate a delay signal providing information about an amount of delay caused by the delay elements to an input signal propagating through the configurable delay circuit; and

a calibration module to evaluate each delay path based on the delay signals from the sampling circuit and identify the delay paths in the configurable delay circuit for emulating critical paths of the data processor at various conditions.

19. A method comprising:

calibrating a configurable delay circuit that has a plurality of delay elements, different combinations of the delay elements representing different delay paths in the configurable delay circuit, the calibration comprising;

evaluating a plurality of delay paths, for each delay path, sending input signals through the delay path, gradually reducing a power supply voltage provided to a data processor and the calibration module until the data processor fails, and evaluating the outputs of a subset of the delay elements corresponding to the delay path when the power supply voltage is at a level that is higher, by a safety margin, than the voltage for which the data processor fails, and identify the delay path as a candidate delay path if the input signal has propagated through some but not all of the subset of delay elements during a sampling time period.

20. The method of claim 19, comprising, if there are more than one candidate delay path, identify a candidate that tracks at least one of temperature or frequency better than the other candidates.

21. The method of claim 19 in which identifying the delay path as a candidate delay path comprises identifying the delay path as a candidate delay path if approximately half of the outputs of the subset of delay elements have logic 1 state and approximately half of the outputs of the subset of delay elements have logic 0 state at the end of the sampling time period.

22. A method comprising:

configuring a configurable delay circuit according to information in a lookup table to select a combination of delay elements to form a delay path, the configurable delay circuit comprising a plurality of delay elements, the lookup table having information for configuring the configurable delay circuit for various conditions;

sampling outputs of a subset of the delay elements associated with the delay path to generate a multi-bit delay signal providing information about an amount of delay caused by the delay elements to an input signal propagating through the delay path, each bit in the multi-bit delay signal indicating whether the input signal has propagated through a corresponding delay element.

23. The method of claim 22, comprising emulating a critical path in a data processor using the delay path in the configurable delay circuit.

24. The method of claim 22, comprising regulating a power supply voltage level provided to a data processor and the configurable delay circuit according to the multi-bit delay signal.

25. The method of claim 24, in which regulating the power supply voltage level comprises regulating the power supply voltage level such that the input signal propagates through approximately half of the subset of the delay elements during a sampling time period.

26. The method of claim 24, comprising at various time points regulating the power supply voltage level based on target voltage values in a look-up table, and in between the time points, regulating the power supply voltage level based on the multi-bit delay signal.