Configuring a tunable inductor across multiple layers of an integrated circuit

• US 8,531,250 B1
• Filed: 03/22/2011
• Issued: 09/10/2013
• Est. Priority Date: 03/22/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Netlogic Microsystems Incorporated (Broadcom, Inc.)
• Inventors: Luschas, Manuel
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US13/069,330
• Time in Patent Office: 903 Days
• Field of Search: 331/167, 331/36.L, 336/200, 257/531
• US Class Current: 331/167
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 21/12 discontinuously variable, e.g. tapped
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1268 switched inductors

Abstract

A system and method for configuring a tunable inductor that minimizes Q factor are provided. The system and method comprise coupling a first inductance, a second inductance, a third inductance, a switch, and two port terminals. The first inductance and the third inductance are coupled between the switch and the port terminals. The second inductance is coupled between the port terminals or between the first and third inductance. The inductances are each disposed on at least one layer, wherein the first inductance is disposed beneath the second inductance and the third inductance is disposed on the same layer as the second inductance. The components are arranged such that toggling the switch tunes the inductance without adversely affecting the Q factor.

Claims

1. An integrated circuit incorporating a tunable inductor comprising:

a plurality of port terminals comprising at least a first port terminal and a second port terminal;

a switch comprising at least a first input and a second input;

a first inductance, comprising at least one winding, coupled to the first port terminal and the first input;

a second inductance, comprising at least one winding, coupled to at least one of the first port terminal and the first inductance and at least one of the second port terminal and a third inductance;

the third inductance, comprising at least one winding, coupled to the second port terminal and the second input;

wherein each of the first inductance and the second inductance is substantially disposed on at least one layer within a first bounded horizontal area, and the first inductance is disposed beneath the second inductance; and

wherein said switch, when closed, couples said first inductance and said third inductance in parallel with said second inductance.

2. The integrated circuit of claim 1, further comprising a plurality of additional layers.

3. The integrated circuit of claim 2, wherein the additional layers are disposed beneath the layers of the first inductance and the second inductance.

4. The integrated circuit of claim 2, wherein the additional layers comprise a bottom ground layer.

5. The integrated circuit of claim 2, wherein the additional layers comprise a bottom ground layer separated from the layers of the first inductance and the second inductance by at least one intermediate layer.

6. The integrated circuit of claim 1, wherein at least one of the first inductor, the second inductor, and the third inductor comprise a plurality of windings fabricated across a plurality of layers.

7. The integrated circuit of claim 6, wherein the windings fabricated across the layers are shorted by a plurality of vertical interconnect access (VIA) elements.

8. The integrated circuit of claim 1, wherein the switch is at least one of a field effect transistor switch and a low-voltage device.

9. The integrated circuit of claim 1, wherein the third inductance is substantially disposed within a second bounded horizontal area adjacent to the first bounded horizontal area.

10. The integrated circuit of claim 1, wherein closing said switch further decreases an inductance value and increases a Q factor of a circuit incorporating the tunable inductor.

11. A method for configuring an integrated circuit incorporating a tunable inductor, the method comprising:

coupling a first inductance, comprising at least one winding, to a first port terminal and a first input to a switch;

coupling a second inductance, comprising at least one winding, to at least one of the first port terminal and the first inductance and at least one of a second port terminal and a third inductance;

coupling the third inductance, the third inductance comprising at least one winding, to the second port terminal and a second input to the switch;

wherein each of the first inductance and the second inductance is substantially disposed on at least one layer within a first bounded horizontal area, and the first inductance is disposed beneath the second inductance; and

wherein said switch, when closed, couples said first inductance and said third inductance in parallel with said second inductance.

12. The method of claim 11, further comprising a plurality of additional layers.

13. The method of claim 12, wherein the additional layers are disposed beneath the layers of the first inductance and the second inductance.

14. The method of claim 12, wherein the additional layers comprise a bottom ground layer.

15. The method of claim 12, wherein the additional layers comprise a bottom ground layer separated from the layers of the first inductance and the second inductance by at least one intermediate layer.

16. The method of claim 11, wherein at least one of the first inductor, the second inductor, and the third inductor comprise a plurality of windings fabricated across a plurality of layers.

17. The method of claim 16, wherein the windings fabricated across the layers are shorted by a plurality of vertical interconnect access (VIA) elements.

18. The method of claim 11, wherein the switch is at least one of a field effect transistor switch and a low-voltage device.

19. The method of claim 11, wherein the third inductance is substantially disposed within a second bounded horizontal area adjacent to the first bounded horizontal area.

20. A voltage controlled oscillator, comprising:

at least one varactor;

at least one capacitor;

a tunable inductor comprising;

a plurality of port terminals comprising at least a first port terminal and a second port terminal;

a switch comprising at least a first input and a second input;

a first inductance, comprising at least one winding, coupled to the first port terminal and the first input;

a second inductance, comprising at least one winding, coupled to at least one of the first port terminal and the first inductance and at least one of the second port terminal and a third inductance;

the third inductance, comprising at least one winding, coupled to the second port terminal and the second input;

wherein each of the first inductance and the second inductance is substantially disposed on at least one layer within a first bounded horizontal area, and the first inductance is disposed beneath the second inductance; and

wherein said switch, when closed, decreases an inductance value and increases a Q factor of said voltage controlled oscillator.

21. The voltage controlled oscillator of claim 20, wherein toggling said switch tunes the resonant frequency of said voltage controlled oscillator.

22. The voltage controlled oscillator of claim 20, wherein the voltage controlled oscillator is configured within a phase-locked loop circuit further comprising:

a voltage source;

a phase frequency detector; and

wherein the voltage source supplies voltage to the varactor and the voltage-controlled oscillator generates an output signal that is received by the phase frequency detector.