Front side implanted guard ring structure for backside illuminated image sensor

• US 8,531,565 B2
• Filed: 02/23/2010
• Issued: 09/10/2013
• Est. Priority Date: 02/24/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Wen-De, Yaung, Dun-Nian, Liu, Jen-Cheng, Chuang, Chun-Chieh, Lin, Jeng-Shyan
• Primary Examiner(s): Ho, Tuan
• Assistant Examiner(s): Chon, Peter
• Application Number:
  US12/710,862
• Publication Number:
  US 20100220226A1
• Time in Patent Office: 1,295 Days
• Field of Search: 348/241, 348/272, 348/294, 348/307, 348/308, 257/126, 257/127, 257/140, 257/170, 257/171, 257/243, 257/244, 257/499, 257/501, 257/506, 257/508, 257/509, 257/510, 438/25, 438/26, 438/42, 438/43, 438/44, 438/45, 438/196, 438/207, 438/208, 438/218, 438/219, 438/220, 438/221, 438/294, 438/295, 438/296, 438/297, 438/318, 438/353, 438/355, 438/356, 438/359, 438/400, 438/404, 438/405, 438/406, 438/412, 438/423
• US Class Current: 348/294
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/14698 Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
• CPC Class Codes: H01L 31/02005 for device characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

An image sensor includes a semiconductor substrate, a guard ring structure in the substrate, and at least one pixel surrounded by the guard ring structure. The guard ring structure is implanted in the substrate by high-energy implantation.

Claims

1. A method of forming a backside illuminated image sensor, the method comprising:

ion-implanting a guard ring structure of a predetermined depth in a front-side surface of a semiconductor substrate, the guard ring structure forming a two-dimensional array of pixels, each pixel of the array of pixels separated from an adjacent pixel by the guard ring structure;

forming at least one image sensing element on the front-side surface of the semiconductor substrate, the at least one image sensing element being formed in a pixel of the array of pixels and surrounded by the guard ring structure; and

reducing a thickness of the semiconductor substrate to a predetermined thickness by removing material from the back-side surface of the semiconductor substrate, wherein the thickness of the semiconductor substrate is reduced until the guard ring structure is co-planar with a back-side surface of the semiconductor substrate, whereby the guard ring structure extends from the front-side surface to the back-side surface of the semiconductor substrate having the reduced thickness.

2. The method of claim 1, further comprising:

annealing the semiconductor substrate with the guard ring structure implanted therein; and

after said annealing, forming a multi-layer interconnect (MLI) structure on the front-side surface of the semiconductor substrate to form electrical connections to the at least one image sensing element.

3. The method of claim 2, wherein the annealing comprises at least one selected from the group consisting of Rapid Thermal Annealing (RTA), laser annealing and furnace annealing.

4. The method of claim 1, wherein said ion-implanting comprises a high-energy ion implantation from the front-side surface towards the back-side surface of the semiconductor substrate.

5. The method of claim 4, wherein said semiconductor substrate includes an epitaxial layer of doped silicon, and wherein the high-energy ion implantation is performed in the epitaxial layer of doped silicon.

6. The method of claim 1, further comprising

forming a control circuit on the front-side surface of the semiconductor substrate, said control circuit being isolated from the at least one image sensing element by the guard ring structure.

7. The method of claim 6, wherein

the control circuit is formed to include a doped well;

and

the guard ring structure is implanted to extend at least as far from the front-side surface of the semiconductor substrate into the semiconductor substrate as said doped well.

8. The method of claim 1, wherein ion-implanting the guard ring structure comprises forming a two-dimensional array of pixels each pixel of the array of pixels separated from an adjacent pixel by the guard ring structure.

9. The method of claim 8, wherein forming the at least one image sensing element comprises forming each of the at least one image sensing element in one pixel of the array of pixels.

10. An image sensor, comprising:

a semiconductor substrate, the substrate having a front-side surface and a back-side surface opposite the front-side surface;

a plurality of image sensing elements formed on the front-side surface of the substrate; and

an ion-implanted guard ring structure separating each of the image sensing elements from other image sensing elements, wherein the guard ring structure extends from the front-side surface of the substrate up to the back-side surface of the substrate and a surface of the guard ring is co-planar with the back-side surface of the substrate.

11. The image sensor according to claim 10, further comprising a multi-layer interconnect (MLI) electrically connected to the image sensing elements.

12. The image sensor according to claim 11, further comprising control circuitry formed on the front-side surface of the substrate and adjacent to the image sensing elements,

wherein said control circuitry is electrically connected to the image sensing elements via the MLI and is separated, within the substrate, from the image sensing elements by the guard ring structure.

13. The image sensor according to claim 12, wherein the control circuitry includes a doped well formed in the front-side surface of the substrate, and wherein a depth of the guard ring structure is greater than or equal to that of the doped well.

14. The image sensor according to claim 13, wherein the doped well of the control circuitry and the guard ring structure are both p-wells.

15. The image sensor according to claim 10, wherein the image sensing elements comprise complementary metal-oxide-semiconductor (CMOS) image sensors.

16. The image sensor according to claim 10, wherein the guard ring structure defines a two-dimensional array of pixels, each pixel of the array of pixels being separated from an adjacent pixel by the guard ring structure, and each of the plurality of image sensing elements being in one pixel of the array of pixels.

17. A method of fabricating an image sensor device, comprising:

forming a guard ring structure in a semiconductor substrate via ion implantation, said guard ring structure dividing the substrate into a two-dimensional array of pixels each pixel of the array of pixels separated from an adjacent pixel by the guard ring structure, wherein a surface of the guard ring structure is co-planar with a back-side surface of the substrate;

forming a plurality of image sensing elements in the substrate, each of the image sensing elements being in one pixel of the two-dimensional array of pixels and surrounded by the guard ring structure; and

annealing the substrate with the guard ring structure and image sensing elements formed therein.

18. The method of claim 17, wherein

said forming the image sensing elements also comprises ion implantation;

and

said annealing removes damage to the substrate caused by the ion implantation during both said forming the image sensing elements and said forming the guard ring structure.

19. The method of claim 17, wherein said annealing is performed prior to any formation of a multi-layer interconnect (MLI) structure for providing electrical connections to the image sensing elements.

20. The method of claim 17, wherein the guard ring structure is implanted in a front-side surface of the substrate to extend farther from the front-side surface into the substrate than any doped well forming any circuitry in the substrate.