Memory cells, memory cell arrays, methods of using and methods of making

• US 8,531,881 B2
• Filed: 05/02/2012
• Issued: 09/10/2013
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US13/462,702
• Publication Number:
  US 20120241708A1
• Time in Patent Office: 496 Days
• Field of Search: 365/185.08, 365/185.05, 365/148
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 63/00 : Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/883 : Oxides or nitrides

Abstract

In at least one embodiment, a memory cell includes a substrate having a top surface and a first conductivity type; a first region having a second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

Claims

1. A semiconductor memory cell comprising:

a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and

a nonvolatile memory comprising a resistance change element configured to store said data stored in said floating body upon transfer thereto.

2. The semiconductor memory cell of claim 1, wherein said resistance change element comprises a phase change material.

3. The semiconductor memory cell of claim 1, wherein said resistance change element comprises a metal-oxide-metal system.

4. The semiconductor memory cell of claim 1, wherein said nonvolatile memory stores said data stored in said floating body upon receiving an instruction to back up said data stored in said floating body.

5. The semiconductor memory cell of claim 1, wherein said nonvolatile memory stores said data stored in said floating body upon a loss of power to said cell, wherein said cell is configured to perform a shadowing process whereby said data in said floating body is loaded into and stored in said nonvolatile memory.

6. The semiconductor memory cell of claim 5, wherein said loss of power to said cell is one of unintentional power loss or intentional power loss, wherein said intentional power loss is predetermined to conserve power.

7. The semiconductor memory cell of claim 5, wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein.

8. The semiconductor memory cell of claim 7, wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.

9. A semiconductor memory cell comprising:

a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and

a nonvolatile memory comprising a resistance change element;

wherein current flowing to said resistance change element flows through said floating body.

10. The semiconductor memory cell of claim 9, wherein said resistance change element comprises a phase change material.

11. The semiconductor memory cell of claim 9, wherein said resistance change element comprises a metal-oxide-metal system.

12. The semiconductor memory cell of claim 9, wherein said nonvolatile memory stores said data stored in said floating body upon receiving an instruction to back up said data stored in said floating body.

13. The semiconductor memory cell of claim 9, wherein said nonvolatile memory stores said data stored in said floating body upon a loss of power to said cell, wherein said cell is configured to perform a shadowing process whereby said data in said floating body is loaded into and stored in said nonvolatile memory.

14. The semiconductor memory cell of claim 13, wherein said loss of power to said cell is one of unintentional power loss or intentional power loss, wherein said intentional power loss is predetermined to conserve power.

15. The semiconductor memory cell of claim 13, wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein.

16. The semiconductor memory cell of claim 15, wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.

17. A semiconductor memory cell comprising:

a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and

a nonvolatile memory comprising a resistance change element,

wherein an amount of current flowing to said resistance change element is determined by said charge stored in said floating body.

18. The semiconductor memory cell of claim 17, wherein said resistance change element comprises a phase change material.

19. The semiconductor memory cell of claim 17, wherein said resistance change element comprises a metal-oxide-metal system.

20. A semiconductor memory array, including:

a plurality of semiconductor memory cells as recited in claim 19, arranged in a matrix of rows and columns.