Memory cells, memory cell arrays, methods of using and methods of making
First Claim
1. A semiconductor memory cell comprising:
- a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and
a nonvolatile memory comprising a resistance change element configured to store said data stored in said floating body upon transfer thereto.
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Accused Products
Abstract
In at least one embodiment, a memory cell includes a substrate having a top surface and a first conductivity type; a first region having a second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.
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Citations
20 Claims
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1. A semiconductor memory cell comprising:
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a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and a nonvolatile memory comprising a resistance change element configured to store said data stored in said floating body upon transfer thereto. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor memory cell comprising:
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a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and a nonvolatile memory comprising a resistance change element; wherein current flowing to said resistance change element flows through said floating body. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A semiconductor memory cell comprising:
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a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and a nonvolatile memory comprising a resistance change element, wherein an amount of current flowing to said resistance change element is determined by said charge stored in said floating body. - View Dependent Claims (18, 19, 20)
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Specification