System and transceiver clocking to minimize required number of reference sources in multi-function cellular applications including GPS

• US 8,532,600 B2
• Filed: 10/30/2012
• Issued: 09/10/2013
• Est. Priority Date: 06/24/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Zaslavsky, Alexander, Brunn, Brian, Uehara, Gregory
• Primary Examiner(s): Tran, Tuan A
• Application Number:
  US13/664,309
• Publication Number:
  US 20130052966A1
• Time in Patent Office: 315 Days
• Field of Search: 455255-265, 4551921-1923, 342 98-103, 342/199, 342/357.62, 342/357.64, 342/357.75, 331/18, 331/34, 331/60
• US Class Current: 455/260
• CPC Class Codes: G01S 19/23 Testing, monitoring, correcting or calibrating of receiver elements
• CPC Class Codes: H03J 1/005 in a loop
• CPC Class Codes: H03J 7/02 Automatic frequency control H03J7/18 takes precedence
• CPC Class Codes: H03J 7/04 where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/22 using more than one loop
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 1/3805 with built-in auxiliary receivers
• CPC Class Codes: H04W 84/12 WLAN [Wireless Local Area Networks]

Abstract

A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.

Claims

1. A system comprising:

a first clock module configured to generate a first clock reference;

a global positioning system (GPS) module configured to operate in response to the first clock reference;

a wireless local area network (WLAN) module configured to operate in response to the first clock reference;

a phase-locked loop (PLL) module configured to generate a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal;

a cellular transceiver configured to receive radio frequency signals from a wireless medium and generate baseband signals in response to the received radio frequency signals; and

a baseband module configured to (i) receive the baseband signals, (ii) operate in response to a selected one of the first clock reference and the second clock reference, and (iii) generate the AFC signal in response to the baseband signals.

2. The system of claim 1 further comprising a selection module configured to (i) receive the first clock reference and the second clock reference and (ii) output the selected one of the first clock reference and the second clock reference to the baseband module.

3. The system of claim 1 further comprising a wireless personal area network (WPAN) module configured to operate in response to the first clock reference.

4. The system of claim 3 wherein the WPAN module comprises a Bluetooth module.

5. The system of claim 3 further comprising a clock distribution module configured to receive the first clock reference and distribute the first clock reference to the GPS module, the WLAN module, the PLL module, and the WPAN module.

6. The system of claim 1, wherein the cellular transceiver comprises a receiver module configured to (i) operate in response to a third clock reference, (ii) receive the radio frequency signals, and (iii) output the baseband signals in response to the radio frequency signals, wherein the radio frequency signals comprise analog radio frequency signals, and wherein the baseband signals comprise digital baseband signals.

7. The system of claim 6, wherein the PLL module is further configured to generate the third clock reference by performing AFC on the first clock reference in response to the AFC signal.

8. The system of claim 7, wherein the third clock reference is a first integer multiple of the second clock reference, the first integer being greater than or equal to one.

9. The system of claim 6, wherein the receiver module comprises:

an analog to digital converter (ADC) configured to (i) operate in response to the third clock reference and (ii) generate digital signals in response to the radio frequency signals; and

a receiver digital signal processor (DSP) configured to (i) operate in response to the third clock reference and (ii) generate the baseband signals in response to the digital signals from the ADC.

10. The system of claim 9, wherein the receiver module further comprises a downconverter configured to (i) operate in response to a fifth clock reference and (ii) generate downconverted signals in response to the radio frequency signals, wherein the ADC generates the digital signals in response to the downconverted signals.

11. The system of claim 10, further comprising a receiver PLL module configured to generate the fifth clock reference in response to the first clock reference.

12. The system of claim 10, further comprising a receiver PLL module configured to generate the fifth clock reference in response to a seventh clock reference from the PLL module.

13. The system of claim 6, wherein the cellular transceiver further comprises a transmitter module configured to (i) operate in response to a fourth clock reference, (ii) receive digital baseband transmit signals, and (iii) output analog radio frequency transmit signals in response to the digital baseband transmit signals.

14. The system of claim 13, wherein the PLL module is further configured to generate the fourth clock reference by performing AFC on the first clock reference in response to the AFC signal.

15. The system of claim 14, wherein the fourth clock reference is a second integer multiple of the second clock reference, the second integer being greater than or equal to one.

16. The system of claim 13, wherein the transmitter module comprises:

a transmitter digital signal processor (DSP) configured to (i) operate in response to the fourth clock reference and (ii) generate intermediate digital signals in response to the digital baseband transmit signals; and

a digital to analog converter (DAC) configured to (i) operate in response to the fourth clock reference and (ii) generate the analog radio frequency transmit signals in response to the intermediate digital signals from the transmitter DSP.

17. The system of claim 16, wherein the transmitter module further comprises an upconverter configured to (i) operate in response to a sixth clock reference and (ii) generate upconverted transmit signals in response to the analog radio frequency transmit signals.

18. The system of claim 17, further comprising a transmitter PLL module configured to generate the sixth clock reference in response to the first clock reference.

19. The system of claim 17, further comprising a transmitter PLL module configured to generate the sixth clock reference in response to an eighth clock reference from the PLL module.

20. The system of claim 1, wherein the PLL module comprises:

a phase frequency detector configured to determine a difference between the first clock reference and an internal clock reference;

a charge pump configured to receive an output of the phase frequency detector;

a filter configured to filter an output of the charge pump;

a voltage controlled oscillator configured to generate the second clock reference;

a divider configured to (i) receive the second clock reference and (ii) output the internal clock reference based on a divisor; and

a fractional adjusting module configured to adjust a ratio of the divisor between two or more integer values during successive intervals.