Method, apparatus and instructions for parallel data conversions
First Claim
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1. A processor comprising:
- a destination storage location corresponding to a first register;
an execution unit having circuitry to process a packed format values by converting a first packed first format value in a first format to a first plurality of second format values, the first packed first format value having at least three sub elements each having a first number of bits, each of the first plurality of second format values being a number represented in a second format and having a second number of bits which is greater than the first number of bits, the execution unit to store all of the first plurality of second format values into the first register.
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Abstract
Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.
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Citations
16 Claims
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1. A processor comprising:
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a destination storage location corresponding to a first register; an execution unit having circuitry to process a packed format values by converting a first packed first format value in a first format to a first plurality of second format values, the first packed first format value having at least three sub elements each having a first number of bits, each of the first plurality of second format values being a number represented in a second format and having a second number of bits which is greater than the first number of bits, the execution unit to store all of the first plurality of second format values into the first register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system comprising:
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a processor including; a destination storage location corresponding to a first register; and an execution unit having circuitry to process a packed format values by converting a first packed first format value in a first format to a first plurality of second format values, the first packed first format value having at least three sub elements each having a first number of bits, each of the first plurality of second format values being a number represented in a second format and having a second number of bits which is greater than the first number of bits, the execution unit to store all of the first plurality of second format values into the first register; a graphics interface coupled to the processor; and a display coupled to the graphics interface. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification