Multipliers with a reduced number of memory blocks

• US 8,533,245 B1
• Filed: 03/03/2010
• Issued: 09/10/2013
• Est. Priority Date: 03/03/2010
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Cheung, Colman C.
• Primary Examiner(s): SUN, SCOTT C
• Application Number:
  US12/716,280
• Time in Patent Office: 1,287 Days
• Field of Search: None
• US Class Current: 708/205
• CPC Class Codes: G06F 1/03 working, at least partly, by table look-up G06F1/025 takes precedence
• CPC Class Codes: G06F 7/523 Multiplying only

Abstract

Techniques for implementing multipliers using memory blocks in an integrated circuit (IC) are provided. The disclosed techniques may reduce the number of memory blocks required to implement various multiplication operations. A plurality of generated products is normalized. The normalized products are scaled to generate a plurality of scaled products. Scaled products with the least root mean square (RMS) error are identified. The scaled products with the least RMS error are then stored in a plurality of memory blocks in an IC. The scaled products may have a reduced number of bits compared to the plurality of generated products that have not been normalized and scaled.

Claims

1. A method for implementing multipliers in an integrated circuit (IC) design, comprising:

generating a plurality of folded products;

normalizing the plurality of folded products to generate a plurality of normalized products;

scaling at least a portion of the plurality of normalized products to generate a plurality of scaled folded products, wherein the scaling reduces a root mean square (RMS) error of the portion of the plurality of normalized products; and

storing the plurality of scaled folded products in a plurality of memory blocks in the IC;

wherein at least one method operation is performed through a processor.

2. The method of claim 1, wherein a plurality of least significant bits (LSBs) of the plurality of normalized products are zeroes, and wherein the stored scaled folded products are utilized in a channel filter application.

3. The method of claim 1, wherein the plurality of memory blocks is a plurality of dual-ported memory blocks.

4. The method of claim 3, further comprising:

storing multiple scaled folded products in at least one of the dual-ported memory blocks.

5. The method of claim 1, wherein the IC design is implemented in a programmable logic device (PLD).

6. The method of claim 1, further comprising:

shifting an output of one of the plurality of memory blocks;

summing the shifted output with another output of one other memory block from the plurality of memory blocks.

7. The method of claim 1, further comprising:

examining a plurality of scaling factors to determine a scaling factor that produces a least RMS error for the portion of the plurality of scaled products; and

selecting the scaled folded products associated with the scaling factor having the least RMS error for the storing.

8. A non-transient machine-readable storage medium encoded with sequences of instructions for processing data, the sequences of instructions which when executed, cause the machine to perform:

multiplying a plurality of filter coefficients with a plurality of data elements to generate a plurality of products, wherein each of the plurality of filter coefficients is multiplied with a corresponding data element;

normalizing the plurality of products;

scaling the plurality of products associated with the plurality of filter coefficients;

examining each of the plurality of products; and

identifying a plurality of scaled products with a least root mean square (RMS) error.

9. The machine-readable storage medium of claim 8, further comprising:

storing the plurality of scaled products in the plurality of memory blocks, wherein some of the plurality of memory blocks are configured to store at least two scaled products each.

10. The machine-readable storage medium of claim 9, further comprising:

designating the plurality of memory blocks to be operated as one of a dual-ported memory block or a single-ported memory block.

11. The machine-readable storage medium of claim 9, further comprising:

shifting an output of the plurality of memory blocks by a number of bits; and

summing the shifted output with another output from the plurality of memory blocks.

12. The machine-readable storage medium of claim 11, wherein the shifting is performed during compilation of the IC.

13. The machine-readable storage medium of claim 8, wherein the scaling the plurality of products includes scaling only a portion of the plurality of products, wherein at least one product with a maximum number of bits is not scaled.

14. The machine-readable storage medium of claim 8, wherein the scaling reduces a total number of bits for each of the plurality of products.

15. A method of implementing multipliers in a plurality of memory blocks for an integrated circuit (IC) design, comprising:

receiving a plurality of first and second operands;

multiplying the first and second operands for each operand pair to generate a plurality of products;

normalizing the plurality of products;

scaling at least a portion of the normalized plurality of products to generate a plurality of scaled products for each of the portion of the normalized plurality of products;

selecting a scaling factor with a least root mean square (RMS) error for each of the plurality of scaled products; and

storing the plurality of scaled products with the least RMS error in a plurality of memory blocks;

wherein at least one method operation is performed through a processor.

16. The method of claim 15, wherein the scaling the at least a portion of the normalized plurality of products includes scaling only a plurality of next-to-center products, wherein a center product with a maximum number of bits is not scaled.

17. The method of claim 15, wherein the plurality of first operands is a plurality of data elements and wherein the plurality of second operands is a plurality of coefficient values.

18. The method of claim 15, further comprising:

storing multiple scaled folded products in at least one of the dual-ported memory blocks.

19. The method of claim 15, further comprising:

determining an RMS error value for each of the plurality of scaled products; and

searching the plurality of scaled products to determine a scaling factor for the least RMS error for each of the plurality of scaled products.

20. The method of claim 15, wherein the method is implemented in an integrated circuit (IC) with a root raised cosine (RRC) filter.

21. The method of claim 15, wherein the IC design is in a form of a netlist implemented in an IC device.