Computing system utilizing dispersed storage

• US 8,533,424 B2
• Filed: 04/06/2010
• Issued: 09/10/2013
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Cleversafe Incorporated (International Business Machines Corporation)
• Inventors: Grube, Gary W., Markison, Timothy W.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US12/755,181
• Publication Number:
  US 20110029742A1
• Time in Patent Office: 1,253 Days
• Field of Search: 711/112, 711/114, 711/5, 711/E12.001, 711/203, 711/E12.058
• US Class Current: 711/203
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A computing system comprises at least a processing module, a main memory, a memory controller, and a plurality of memory components. A method begins by the memory controller receiving a memory access request regarding a data segment. The method continues with the memory controller interpreting the memory access request to determine whether an error encoding dispersal function of the data segment is applicable. The method continues with the memory controller identifying at least a threshold number of memories based on the memory access request, wherein the threshold number of memories includes at least one of the main memory and/or one or more of the plurality of memory components, when the error encoding dispersal function is applicable. The method continues with the memory controller addressing the at least a threshold number of memories to facilitate the memory access request.

Claims

1. A computing system comprises:

a computing core that includes;

a processing module;

main memory; and

a memory controller coupled to the processing module and to the main memory; and

a plurality of memory components operably coupled to the computing core, wherein the memory controller is operable to;

receive a memory access request regarding a data segment;

interpret the memory access request to determine whether an error encoding dispersal function of the data segment is applicable;

when the error encoding dispersal function is applicable;

identify at least a threshold number of memories based on the memory access request, wherein memories of the threshold number of memories includes at least one of;

the main memory; and

one or more of the plurality of memory components; and

address the at least a threshold number of memories to facilitate the memory access request

when the error encoding dispersal function is not applicable;

identify one of the memories; and

address the one of the memories to facilitate the memory access request.

2. The computing system of claim 1, wherein the memory access request comprises at least one of:

a read instruction;

a write instruction;

a delete instruction;

a modify instruction; and

a list instruction.

3. The computing system of claim 1, wherein the memory controller is further operable to, when the memory access request includes a write instruction and the error encoding dispersal function is applicable:

encode the data segment to produce an encoded data segment;

slice the encoded data segment to produce a plurality of slices; and

address the at least a threshold number of memories to store the plurality of slices.

4. The computing system of claim 1, wherein the plurality of memory components comprises at least one of:

one or more local hard disk drives;

one or more local solid state memory devices;

one or more local area network (LAN) memory devices; and

one or more wide area network (WAN) memory devices.

5. The computing system of claim 1, wherein the memory controller further functions to:

convert a virtual memory address of the data segment to one or more physical addresses within the at least a threshold number of the memories to produce a virtual to physical mapping; and

facilitate storage of the virtual to physical memory mapping.

6. The computing system of claim 1, wherein the memory controller further functions to:

identify at least a threshold number of the plurality of memory components based on the memory access request to produce the at least a threshold number of memories; and

address the at least a threshold number of the plurality of memory components to facilitate the memory access request.

7. The computing system of claim 1, wherein the main memory comprises:

a plurality of main memory components, wherein the memory controller further functions to;

identify at least a threshold number of the plurality of main memory components based on the memory access request to produce the at least a threshold number of memories; and

address the at least a threshold number of the plurality of main memory components to facilitate the memory access request.

8. The computing system of claim 1, wherein the memory controller further functions to:

identify the at least a threshold number of memories based on the memory access request, wherein the threshold number of memories includes;

the main memory corresponding to a first pillar of distributed storage; and

a local non-core memory corresponding to a second pillar of distributed storage.

9. The computing system of claim 1, wherein the plurality of memory components comprises:

a plurality of local non-core memory components, wherein the memory controller further functions to;

identify at least a threshold number of the plurality of local non-core memory components based on the memory access request, wherein a first non-core memory component of the plurality of memory components corresponds to a first pillar of distributed storage and a second non-core memory component of the plurality of memory components corresponds to a second pillar of distributed storage.

10. The computing system of claim 9, wherein the plurality of memory components comprises:

a plurality of non-local memory components, wherein the memory controller further functions to facilitate a transfer of a plurality of slices of the data segment between the at least threshold number of the plurality of local non-core memory components and the plurality of non-local memory components.

11. A computing core comprises:

a processing module;

a plurality of memory interfaces operable to couple to a plurality of memory components;

main memory; and

a memory controller coupled to the processing module, the plurality of memory interfaces, and to the main memory, wherein the memory controller is operable to;

receive a memory access request regarding a data segment;

interpret the memory access request to determine whether an error encoding dispersal function of the data segment is applicable;

when the error encoding dispersal function is applicable;

identify at least a threshold number of memories based on the memory access request, wherein memories of the threshold number of memories includes at least one of;

the main memory; and

one or more of the plurality of memory components; and

address the at least a threshold number of memories to facilitate the memory access request

when the error encoding dispersal function is not applicable;

identifying one of the memories; and

addressing the one of the memories to facilitate the memory access request.

12. The computing core of claim 11, wherein the memory access request comprises at least one of:

a read instruction;

a write instruction;

a delete instruction;

a modify instruction; and

a list instruction.

13. The computing core of claim 11, wherein the memory controller is further operable to, when the memory access request includes a write instruction and the error encoding dispersal function is applicable:

encode the data segment to produce an encoded data segment;

slice the encoded data segment to produce one or more slices; and

address, via at least one of the plurality of memory interfaces, the at least a threshold number of memories to store the plurality of slices.

14. The computing core of claim 11, wherein the memory controller further functions to:

convert a virtual memory address of the data segment to one or more physical addresses within the at least a threshold number of the memories to produce a virtual to physical mapping; and

facilitate storage of the virtual to physical memory mapping.

15. The computing core of claim 11, wherein the memory controller further functions to:

identify at least a threshold number of the plurality of memory components based on the memory access request to produce the at least a threshold number of memories; and

address, via at least one of the plurality of memory interfaces, the at least a threshold number of the plurality of memory components to facilitate the memory access request.

16. The computing core of claim 11, wherein the main memory comprises:

a plurality of main memory components, wherein the memory controller further functions to;

identify at least a threshold number of the plurality of main memory components based on the memory access request to produce the at least a threshold number of memories; and

address the at least a threshold number of the plurality of main memory components to facilitate the memory access request.

17. The computing core of claim 11, wherein the memory controller further functions to:

identify the at least a threshold number of memories based on the memory access request, wherein the threshold number of memories includes;

the main memory corresponding to a first pillar of distributed storage; and

a local non-core memory corresponding to a second pillar of distributed storage.

18. The computing core of claim 11, wherein the plurality of memory components comprises:

a plurality of local non-core memory components, wherein the memory controller further functions to;

identify at least a threshold number of the plurality of local non-core memory components based on the memory access request, wherein a first non-core memory component of the plurality of memory components corresponds to a first pillar of distributed storage and a second non-core memory component of the plurality of memory components corresponds to a second pillar of distributed storage.

19. The computing core of claim 18, wherein the plurality of memory components comprises:

a plurality of non-local memory components, wherein the memory controller further functions to facilitate a transfer of a plurality of slices of the data segment between the at least threshold number of the plurality of local non-core memory components and the plurality of non-local memory components.