Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

• US 8,533,431 B2
• Filed: 10/15/2008
• Issued: 09/10/2013
• Est. Priority Date: 03/22/2001
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Master, Paul L., Hogenauer, Eugene, Scheuermann, Walter James
• Primary Examiner(s): Caldwell, Andrew
• Assistant Examiner(s): PARTRIDGE, WILLIAM B
• Application Number:
  US12/251,903
• Publication Number:
  US 20090037692A1
• Time in Patent Office: 1,791 Days
• Field of Search: 712/15, 712/29
• US Class Current: 712/15
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Claims

1. An adaptive computing engine comprising:

a plurality of computational matrices, at least one of the computational matrices comprising a plurality of heterogeneous computational elements, at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components; and

an interconnection network coupling the plurality of computational matrices to each other,

the interconnection network for transmitting data between the plurality of computational matrices, and for transmitting configuration information to at least one of the plurality of computational matrices, the configuration information for configuring the at least one of the plurality of computational matrices to perform a first function and for reconfiguring the at least one of the plurality of computational matrices to perform a second function.

2. The adaptive computing engine of claim 1, wherein the plurality of computational matrices includes a plurality of computational units.

3. The adaptive computing engine of claim 2, wherein the plurality of computational units is heterogeneous, the plurality of computational units having a first computational unit with a first computational architecture and a second computational unit with a second different computational architecture.

4. The adaptive computing engine of claim 2, wherein the interconnection network includes switchable interconnections between the plurality of computational units, wherein the computational matrices are configured via switching the interconnections between the computational units in response to the configuration information.

5. The adaptive computing engine of claim 4, wherein the computational units include a plurality of the computational elements.

6. The adaptive computing engine of claim 5, wherein the interconnection network includes switchable interconnections between the plurality of computational elements, wherein the computational units are configured via switching the interconnections between the computational elements in response to the configuration information.

7. The adaptive computing engine of claim 1, wherein the interconnection network transmits control signals to at least one of the plurality of computational matrices.

8. The adaptive computing engine of claim 2, wherein the interconnection network includes interconnections between the computational units, the interconnection network having denser interconnections between the computational units than the interconnections between the computational matrices.

9. A method of distributing configuration information and data between a plurality of heterogeneous computational elements coupled to each other via an interconnection network, at least two of the heterogeneous computational elements each performing an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, to perform a function, the method comprising:

transmitting configuration information to at least one of the plurality of computational elements, the configuration information used to configure the interconnections between at least one of the plurality of heterogeneous computational elements to perform a first function and to reconfigure the at least one of the plurality of heterogeneous computational elements to perform a second function; and

transmitting data between the plurality of heterogeneous computational elements via the interconnection network.

10. The method of claim 9, wherein the interconnection network transmits control signals to at least one of the plurality of computational elements.

11. The method of claim 9, further comprising:

organizing the plurality of computational elements in a computational unit;

coupling a second interconnection network between the computational unit and other components;

wherein the interconnection network has denser interconnections between the computational elements than the second interconnection network has between the computational unit and the other components.

12. An adaptive computing engine comprising:

a plurality of heterogeneous computational elements each for performing an arithmetic operation and each having components in a fixed architecture with fixed connections between the components;

an interconnection network coupling the plurality of heterogeneous computational elements to each other, the interconnection network including switchable connections between the plurality of computational elements,

the interconnection network for transmitting data between the plurality of heterogeneous computational elements, and for accepting configuration information to change the switchable connections between at least some of the plurality of heterogeneous computational elements, the configuration information for configuring switchable connections between the plurality of heterogeneous computational elements to perform a first function and for reconfiguring the switchable connections between the at least some of the plurality of heterogeneous computational elements to perform a second function.