Clock switching circuits and methods to select from multiple clock sources

• US 8,533,517 B2
• Filed: 02/28/2009
• Issued: 09/10/2013
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: NPX B.V.
• Original Assignee: Synopsys Incorporated
• Inventors: Gregie, Neil, Vos, Antonius Maria Hubertus
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US12/919,099
• Publication Number:
  US 20110026656A1
• Time in Patent Office: 1,655 Days
• Field of Search: 713500-501, 713300-340, 327/99
• US Class Current: 713/500
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency

Abstract

For use in systems having multiple potential clock sources, circuitry and methods are used for selecting from among multiple clock sources and for preventing switching to an inactive clock source. Such clock switching circuitry and methods are used to detect an activity-status indication of the clock sources, generate a selection based update-enable signal responsive to the detected activity-status indication of the selected clock source, update a clock select input signal in response to a clock switch request for switching to the selected clock source and based on the generated selection based update-enable signal, and control switching to the selected clock source based on the updated clock select input signal.

Claims

1. A method for switching between a plurality of clock sources comprising:

receiving a select signal indicating selection of a clock source among the plurality of clock sources;

detecting an activity-status indication representing that the selected clock source is active or inactive;

generating an enable signal for the selected clock source responsive to receiving the select signal and detecting that the selected clock source is active;

in response to receiving a clock switch request instructing switching to the selected clock source and receiving the enable signal, updating a clock select input signal to indicate switching to the selected clock source; and

switching to the selected clock source in response to receiving the updated clock select input signal.

2. The method of claim 1, further comprising detecting that clock sources other than the selected clock source are active or inactive.

3. The method of claim 1, wherein generating the enable signal includes generating a selection-enable signal when the selected clock source is indicated as active, and generating a selection-disable signal when the selected clock source is indicated as inactive.

4. The method of claim 1, wherein switching to the selected clock source includes using the clock select input signal as a control input of a multiplexer that selects from among the plurality of clock sources.

5. The method of claim 1, wherein the plurality of clock sources include at least one internal clock source and at least one external clock source.

6. The method of claim 1, wherein the plurality of clock sources include clock sources having different phases.

7. The method of claim 1, further comprising receiving a switching-status signal indicating whether the clock switch request was allowed or prevented responsive to determining whether to switch to the selected clock source.

8. The method of claim 1, wherein the plurality of clock sources include clock sources having different frequencies.

9. The method of claim 3, further comprising storing a clock value representative of the clock select input signal in a select register, and wherein updating the clock select input signal comprises overwriting the clock value in the select register to identify the selected clock source in response to generating the enable signal for the selected clock.

10. The method of claim 3, further comprising storing a clock value representative of the clock select input signal in a select register, and wherein updating the clock select input signal comprises preventing overwriting of the clock value in the select register in response to not generating the enable signal.

11. A circuit for switching between a plurality of clock sources comprising:

detection circuitry configured to detect an activity-status indication representing that a selected clock source is active or inactive;

update-enable circuitry configured to;

receive a select signal indicating selection of the selected clock source; and

generate an enable signal for the selected clock source responsive to receiving the select signal and detecting that the selected clock source is active;

control circuitry configured to update a clock select input signal to indicate switching to the selected clock source responsive to receiving a clock switch request instructing switching to the selected clock source and receiving the enable signal; and

switching circuitry configured to switch to the selected clock source in response to receiving the updated clock select input signal.

12. The circuit of claim 11, wherein the detection circuitry further comprises a plurality of detectors, each detector associated with one of the multiple clock sources and configured to produce a logical 1 if the associated clock source is active and a logical 0 if the associated clock source is inactive.

13. The circuit of claim 11, wherein the update-enable circuitry further comprises a plurality of comparators configured to compare the clock select input signal with static values associated with the plurality of clock sources.

14. The circuit of claim 11, wherein the control circuitry further comprises a multiplexer configured to select between overwriting a clock value in a select register to reflect the selected clock source and maintaining the clock value in the select register to reflect a current clock source, the value in the select register representing the updated clock select input signal.

15. The circuit of claim 11, wherein the switching circuitry includes a multiplexer configured to select an output clock source from among the plurality of clock sources in response to receiving the updated clock select input signal.

16. The circuit of claim 11, wherein the plurality of clock sources include at least one internal clock source and at least one external clock source.

17. The circuit of claim 11, wherein the plurality of clock sources include clock sources having different phases.

18. The circuit of claim 11, wherein the plurality of clock sources include clock sources having different frequencies.