Method for adjusting phase of a clock in a host based upon comparison of first and second pattern signals from a memory and the first and the second pattern signals pre-stored in the host

• US 8,533,521 B2
• Filed: 09/14/2012
• Issued: 09/10/2013
• Est. Priority Date: 12/26/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fujimoto, Akihisa
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Chen, Xuxing
• Application Number:
  US13/619,724
• Publication Number:
  US 20130019119A1
• Time in Patent Office: 361 Days
• Field of Search: 713/401, 713/503
• US Class Current: 713/503
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.

Claims

1. A memory device comprising:

a nonvolatile semiconductor memory unit;

a memory controller configured to perform control to receive a command signal, to send a response signal, and to send and receive a data signal, and a status signal in synchronization with a clock signal, wherein the memory controller controls receiving of the command signal and sending of the response signal through a command line from and to a host device to which the memory device is connected, controls sending and receiving of the data signal and the status signal through a data line to and from the host device, and controls receiving of the clock signal through a clock line from the host device; and

a memory-side pattern signal storage unit configured to store first and second tuning pattern signals to be sent to the host device, the first and second tuning pattern signals being used by the host device to adjust a phase of the clock signal for use as a sampling clock signal;

wherein;

the first and second tuning pattern signals are pre-stored also in the host device; and

the memory controller sends to the host device the first tuning pattern signal and the second tuning pattern signal, and a time period during which the first tuning pattern signal is sent and a time period during which the second tuning pattern signal is sent overlap each other.

2. The memory device according to claim 1, wherein the first tuning pattern signal and the second tuning pattern signal each includes a CRC code.

3. The memory device according to claim 2, wherein the first and second tuning pattern signals enable detection of interference between lines.

4. The memory device according to claim 3, wherein the memory-side pattern signal storage unit stores a plurality of tuning pattern signal sets, each including the first and second tuning pattern signals and being pre-stored also in the host device, and one of the plurality of tuning pattern signal sets is selected and sent to the host device in response to a command from the host device.

5. The memory device according to claim 4, further comprising a synchronization header signal output unit configured to output a synchronization header signal to be added to the data signal, the response signal, and the status signal and sent to the host device for the host device to fine-adjust a phase of the sampling clock signal.

6. The memory device according to claim 5, wherein the synchronization header signal is a 4-bit signal including data “

0101”

.

7. The memory device according to claim 6, wherein the memory controller sends the first and second tuning pattern signals as the response signal and the data signal in response to receipt of a tuning command as the command signal from the host device.

8. The memory device according to claim 7, wherein the nonvolatile semiconductor memory unit is a NAND flash memory unit.

9. The memory device according to claim 8, which is a memory card.

10. A host device comprising:

a clock configured to generate a clock signal;

a host controller configured to perform control to send a command signal and a data signal in synchronization with the clock signal to a memory device including a nonvolatile semiconductor memory unit and being connected to the host device and to receive from the memory device a response signal, a data signal, and a status signal in synchronization with a sampling clock signal, the sampling clock signal being the clock signal whose phase is adjusted, wherein the host controller controls sending of the command signal and receiving of the response signal through a command line, controls sending and receiving of the data signal through a data line, controls receiving of the status signal through a data line, and controls sending of the clock signal through a clock line;

a sampling clock adjustment unit configured to adjust a phase of the sampling clock signal; and

a host-side pattern signal storage unit configured to pre-store first and second tuning pattern signals that are pre-stored also in the memory device and sent from the memory device for adjusting the phase of the sampling clock signal;

the host device further comprising;

an interference detecting unit configured to compare the first tuning pattern signal received from the memory device and the second tuning pattern signal received from the memory device in a time period overlapping a time period during which the first tuning pattern signal is received with the first and second tuning pattern signals pre-stored in the host-side pattern signal storage unit to detect whether there is a difference;

wherein the sampling clock adjustment unit adjusts the phase of the sampling clock based on a detection result by the interference detecting unit.

11. The host device according to claim 10, wherein the first tuning pattern signal and the second tuning pattern signal each includes a CRC code.

12. The host device according to claim 11, wherein the host-side pattern signal storage unit stores a plurality of tuning pattern signal sets, each including the first and second tuning pattern signals and pre-stored also in the memory device, and an instruction as to which of the plurality of tuning pattern signals sets is to be used is sent to the memory device with the command signal.

13. The host device according to claim 12, further comprising a sampling clock fine-adjustment unit configured to fine-adjust the phase of the sampling clock signal on the basis of a synchronization header signal added to the data signal or the command signal received from the memory device.

14. The host device according to claim 13, wherein the nonvolatile semiconductor memory unit of the memory device is a NAND flash memory unit.

15. The host device according to claim 14, wherein the memory device is a memory card.