Method and system for trusted/untrusted digital signal processor debugging operations
First Claim
1. A method, comprising:
- determining a debug mode of one or more threads of a multi-threaded processor based on a trust value stored at a system configuration register; and
providing a first set of debugging features and privileges when the debug mode is a first debug mode and a second set of debugging features and privileges when the debug mode is a second debug mode,wherein providing the first set of debugging features and privileges includes granting unrestricted write control for a debugging command register, andwherein providing the second set of debugging features and privileges includes restricting writing any command to the debugging command register other than an interrupt command.
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Accused Products
Abstract
Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.
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Citations
30 Claims
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1. A method, comprising:
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determining a debug mode of one or more threads of a multi-threaded processor based on a trust value stored at a system configuration register; and providing a first set of debugging features and privileges when the debug mode is a first debug mode and a second set of debugging features and privileges when the debug mode is a second debug mode, wherein providing the first set of debugging features and privileges includes granting unrestricted write control for a debugging command register, and wherein providing the second set of debugging features and privileges includes restricting writing any command to the debugging command register other than an interrupt command. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A system comprising:
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a system configuration register having a core processor control bit, the core processor control bit operative to determine a debug mode of one or more threads of a multi-threaded processor; and instructions for providing a first set of debugging features and privileges when the debug mode is a first debug mode and a second set of debugging features and privileges when the debug mode is a second debug mode, wherein the instructions for providing the first set of debugging features and privileges include instructions for granting unrestricted write control for a debugging command register, and wherein the instructions for providing the second set of debugging features and privileges include instructions for restricting writing any command to the debugging command register other than an interrupt command. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A multi-threaded digital signal processor comprising:
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means for determining a debug mode of one or more threads of a multi-threaded processor based on a trust value stored at a system configuration register; and means for providing a first set of debugging features and privileges when the debug mode is a first debug mode and a second set of debugging features and privileges when the debug mode is a second debug mode, wherein the means for providing the first set of debugging features and privileges include means for granting unrestricted write control for a debugging command register, and wherein the means for providing the second set of debugging features and privileges include means for restricting writing any command to the debugging command register other than an interrupt command. - View Dependent Claims (27, 28, 29)
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30. A non-transitory computer usable medium having computer readable program code means embodied therein for processing instructions on a multi-threaded digital signal processor for debugging the multi-threaded digital signal processor, the computer usable medium comprising:
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computer readable program code means for determining a debug mode of one or more threads of a multi-threaded processor based on a trust value stored at a system configuration register; and computer readable program code means for providing a first set of debugging features and privileges when the debug mode is a first debug mode and a second set of debugging features and privileges when the debug mode is a second debug mode, wherein the computer readable program code means for providing the first set of debugging features and privileges include computer readable program code means for granting unrestricted write control for a debug in command register, and wherein the computer readable program code means for providing the second set of debugging features and privileges include computer readable program code means for restricting writing any command to the debugging command register other than an interrupt command.
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Specification