Continuous application and decompression of test patterns and selective compaction of test responses
First Claim
1. A system, comprising:
- a circuit comprising a register and a decompressor, the decompressor comprising a linear feedback shift register (LFSR); and
automatic testing equipment located external to the circuit,wherein the register is configured to load compressed test pattern data from an output of the automatic testing equipment and to output the compressed test pattern data to an input logic gate of the LFSR, the input logic gate of the LFSR being configured to receive the compressed test pattern data and logically combine the compressed test pattern data with data stored within the LFSR.
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Accused Products
Abstract
A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
162 Citations
11 Claims
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1. A system, comprising:
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a circuit comprising a register and a decompressor, the decompressor comprising a linear feedback shift register (LFSR); and automatic testing equipment located external to the circuit, wherein the register is configured to load compressed test pattern data from an output of the automatic testing equipment and to output the compressed test pattern data to an input logic gate of the LFSR, the input logic gate of the LFSR being configured to receive the compressed test pattern data and logically combine the compressed test pattern data with data stored within the LFSR. - View Dependent Claims (2, 3, 4, 5)
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6. A method, comprising:
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loading a register within a circuit with compressed test pattern bits; transferring the compressed test pattern bits from the register to a decompressor comprising a linear feedback shift register (LFSR); and decompressing the compressed test pattern bits with the decompressor, wherein the decompressing comprises logically combining the compressed test pattern bits with bits stored within the decompressor. - View Dependent Claims (7, 8, 9, 10, 11)
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Specification