Cache controller and cache controlling method
First Claim
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1. A cache memory controller comprising:
- a data detecting unit that detects a write address of a cache memory into which store data is to be stored including first store data to be stored in the cache memory and second store data not to be stored in the cache memory, the data detecting unit holding the first store data in a store buffer, when the store data is transmitted from an execution unit;
a data determining unit that determines whether first existing data to be overwritten by the first store data and second existing data not to be overwritten by the second store data exist in the write address of the cache memory;
an existing data obtaining unit that obtains the second existing data, and holds the obtained second existing data in a fetch register when the data determining unit determines that the second existing data exists in the write address of the cache memory;
a store data writing unit that concatenates the first store data held in the store buffer and the second existing data held in the fetch register to generate concatenated store data, stores the generated concatenated store data in a write buffer and writes the concatenated store data stored in the write buffer into the write address of the cache memory; and
an ECC generating unit that generates an error correcting code of the concatenated store data written in the write address of the cache memory.
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Abstract
A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in the FCDR, and merges the stored data with data-to-be-stored in the store data output from the execution unit and stored in the STBs or the WBs to generate new store data. The cache memory controlling unit then writes the generated new store data in the DATA-RAM, generates an ECC from the new store data, and writes the ECC in the ECC-RAM.
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Citations
6 Claims
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1. A cache memory controller comprising:
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a data detecting unit that detects a write address of a cache memory into which store data is to be stored including first store data to be stored in the cache memory and second store data not to be stored in the cache memory, the data detecting unit holding the first store data in a store buffer, when the store data is transmitted from an execution unit; a data determining unit that determines whether first existing data to be overwritten by the first store data and second existing data not to be overwritten by the second store data exist in the write address of the cache memory; an existing data obtaining unit that obtains the second existing data, and holds the obtained second existing data in a fetch register when the data determining unit determines that the second existing data exists in the write address of the cache memory; a store data writing unit that concatenates the first store data held in the store buffer and the second existing data held in the fetch register to generate concatenated store data, stores the generated concatenated store data in a write buffer and writes the concatenated store data stored in the write buffer into the write address of the cache memory; and an ECC generating unit that generates an error correcting code of the concatenated store data written in the write address of the cache memory. - View Dependent Claims (2, 3)
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4. A cache memory controlling method comprising:
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detecting a write address of a cache memory into which store data is to be stored including first store data to be stored in the cache memory and second store data not to be stored in the cache memory, and holding the first store data in a store buffer when the store data is transmitted from an execution unit; determining whether first existing data to be overwritten by the first store data and second existing data not to be overwritten by the second store data exist in the write address of the cache memory; obtaining the second existing data, and holding the obtained second existing data into a fetch register when the determining determines that the second existing data exists in the write address of the cache memory; concatenating the first store data held in the store buffer and the obtained second existing data held in the fetch register to generate concatenated store data, storing the generated concatenate store data in a write buffer and writing the concatenated store data stored in the write buffer into the write address of the cache memory; and generating an error correcting code of the concatenated store data written in the write address of the cache memory. - View Dependent Claims (5, 6)
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Specification