Apparatus, system, and method for managing data using a data pipeline

• US 8,533,569 B2
• Filed: 08/30/2012
• Issued: 09/10/2013
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Unification Technologies LLC (Acacia Research Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Flynn, David, Lagerstedt, Bert, Strasser, John, Thatcher, Jonathan, Zappe, Michael
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US13/600,077
• Publication Number:
  US 20120324311A1
• Time in Patent Office: 376 Days
• Field of Search: 714/758, 714/769, 714/773, 711/102, 711/104
• US Class Current: 714/769
• CPC Class Codes: G06F 1/183 Internal mounting support structures, e.g. for printed circuit boards, internal connecting means for buses G06F13/409
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: G06F 2211/002 Bus
• CPC Class Codes: G06F 2211/103 Hybrid, i.e. RAID systems with parity comprising a mix of RAID types
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/70 Details relating to dynamic memory management
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 : Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0604 : Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0608 : Saving storage space on storage systems
• CPC Class Codes: G06F 3/0613 : in relation to throughput
• CPC Class Codes: G06F 3/0619 : in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0643 : Management of files
• CPC Class Codes: G06F 3/065 : Replication mechanisms
• CPC Class Codes: G06F 3/0652 : Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0656 : Data buffering arrangements
• CPC Class Codes: G06F 3/0659 : Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 : Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/52 : Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/54 : Interprogram communication
• CPC Class Codes: H04L 67/02 : based on web technology, e.g. hypertext transfer protocol [HTTP]
• CPC Class Codes: H04L 67/1097 : for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H05K 7/1444 : Complex or three-dimensional-arrangements; Stepped or dual mother boards
• CPC Class Codes: H05K 7/1487 : Blade assemblies, e.g. blade cases or inner arrangements within a blade
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, system, and method are disclosed for managing data in a solid-state storage device. A solid-state storage and solid-state controller are included. The solid-state storage controller includes a write data pipeline and a read data pipeline The write data pipeline includes a packetizer and an ECC generator. The packetizer receives a data segment and creates one or more data packets sized for the solid-state storage. The ECC generator generates one or more error-correcting codes (“ECC”) for the data packets received from the packetizer. The read data pipeline includes an ECC correction module, a depacketizer, and an alignment module. The ECC correction module reads a data packet from solid-state storage, determines if a data error exists using corresponding ECC and corrects errors. The depacketizer checks and removes one or more packet headers. The alignment module removes unwanted data, and re-formats the data as data segments of an object.

Claims

1. A method of reading data, the method comprising:

receiving a read request for data stored on a solid-state storage device comprising two or more solid-state storage elements;

reading, through a read data pipeline, an error-correcting code (ECC) block, a first portion of the ECC block read from a page of a first one of the solid-state storage elements and a second portion of the ECC block read from a page of a second one of the solid-state storage elements; and

detecting an error in the ECC block;

in response to detecting the error, determining whether the error is correctable.

2. The method of claim 1, further comprising:

correcting the error in response to determining that the error is correctable; and

providing the requested data to a requesting device, the requested data comprising at least a portion of the ECC block.

3. The method of claim 2, wherein providing the requested data further comprises:

depacketizing one or more packets of the ECC block by checking and removing one or more packet headers, the one or more packets of the ECC block comprising the requested data; and

re-formatting the requested data in a form compatible with the requesting device; and

transmitting the requested data to the requesting device.

4. The method of claim 1, wherein the first portion of the ECC block comprises the requested data and the second portion of the ECC block comprises the error-correcting code capable of correcting an error in the requested data.

5. The method of claim 1, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a block size of the requested data.

6. The method of claim 1, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a physical page size of the solid-state storage elements.

7. The method of claim 1, wherein a length of the error-correcting code is predetermined based on one of a performance metric, an efficiency metric, and a data integrity metric.

8. The method of claim 1, wherein each solid-state storage element comprises a plurality of erase blocks and wherein the ECC block is one of a plurality of ECC blocks, wherein the ECC blocks divide evenly within the erase blocks.

9. An apparatus for reading data, the apparatus comprising:

a first and a second solid-state storage element; and

a read data pipeline configured to read an error-correcting code (ECC) block from the solid-state storage elements, the ECC block comprising at least a portion of data requested by a requesting device and an error-correcting code capable of correcting an error in the ECC block, wherein reading the ECC block comprises reading a first portion of the ECC block from a page of the first solid-state storage element and a second portion from a page of the second solid-state storage element, the read data pipeline comprising, an ECC correction module configured to detect an error in the ECC block read from the solid-state storage elements; and

an alignment module configured to format the portion of the requested data in the ECC block for transmittal to the requesting device.

10. The apparatus of claim 9, wherein the read data pipeline comprises a depacketizer configured to depacketize one or more packets of the ECC block by checking and removing one or more packet headers, the one or more packets of the ECC block comprising the portion of the requested data, the ECC block having no fixed relationship between a size of the one or more packets and a size of the ECC block;

wherein the ECC correction module is configured to correct the error.

11. The apparatus of claim 9, wherein the read data pipeline further comprises a decryption module configured to decrypt the portion of the requested data using an encryption key received from the requesting device in conjunction with a read request.

12. The apparatus of claim 9, further comprising a read synchronization buffer configured to buffer the ECC block read from the solid-state storage elements prior to processing by the read data pipeline, the read synchronization buffer disposed at a boundary between a solid-state storage clock domain and a local bus clock domain.

13. The apparatus of claim 9, wherein the first portion and the second portion are stored on the first and the second solid-state storage elements responsive to a single solid-state storage element page programming command.

14. The apparatus of claim 9, wherein the read data pipeline accesses the first and the second solid-state storage elements in parallel via a bi-directional storage input/output bus.

15. The apparatus of claim 9, wherein the first portion of the ECC block comprises a portion of the received data and the second portion of the ECC block comprises the error-correcting code capable of correcting an error in the portion of the received data.

16. The apparatus of claim 9, wherein each solid-state storage element comprises a plurality of erase blocks, and wherein the ECC block is one of a plurality of ECC blocks configured to divide evenly within the erase blocks.

17. A non-transitory computer readable medium having program instructions stored thereon, wherein the program instructions are executable by a computer system to cause the computer system to perform operations comprising:

receiving a read request from a requesting device for data stored on a solid-state storage device comprising two or more solid-state storage elements and a read data pipeline;

reading, with the read data pipeline, an error-correcting code (ECC) block comprising at least a portion of the requested data and an error-correcting code capable of correcting an error in the ECC block, wherein reading the ECC block comprises reading a first portion of the ECC block from a page of a first one of the solid-state storage elements and a second portion from a page of a second one of the solid-state storage elements; and

providing at least the portion of the requested data to the requesting device.

18. The non-transitory computer readable medium of claim 17, wherein the first portion of the ECC block comprises the portion of the requested data and the second portion of the ECC block comprises the error-correcting code capable of correcting an error in the portion of the requested data.

19. The non-transitory computer readable medium of claim 17, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a physical page size of the solid-state storage elements.

20. The non-transitory computer readable medium of claim 17, wherein each solid-state storage element comprises a plurality of erase blocks and wherein the ECC block is one of a plurality of ECC blocks, wherein the ECC blocks divide evenly within the erase blocks.

21. A system for reading data, the system comprising:

a solid-state storage device comprising two or more solid-state storage elements; and

a solid-state storage controller communicatively coupled to the two or more solid-state storage elements, the solid-state storage device comprising, a read data pipeline configured to read an error-correcting code (ECC) block from the solid-state storage elements, the ECC block comprising at least a portion of data requested by a requesting device and an error-correcting code capable of correcting an error in the ECC block, wherein reading the ECC block comprises reading a first portion of the ECC block from a first one of the solid-state storage elements and reading a second portion from a second one of the solid-state storage elements, the read data pipeline comprising, an ECC correction module configured to correct an error in the ECC block read from the solid-state storage elements;

a depacketizer configured to access the portion of the requested data in the ECC block; and

an alignment module configured to reformat the portion of the requested data in the ECC block to a form compatible with the requesting device.

22. The system of claim 21, further comprising a computer and a system bus, the solid-state storage device coupled to the computer through the system bus.

23. The system of claim 21, wherein a length of the error-correcting code is predetermined to correct a particular number of bit errors in the ECC block and the length of the error-correcting code is predetermined independent of a physical page size of the solid-state storage elements.

24. The system of claim 21, wherein the read data pipeline is configured to read a plurality of ECC blocks comprising the requested data from the solid-state storage elements, wherein the ECC correction module is configured to resolve correct errors of each of the plurality of ECC blocks, and wherein the depacketizer is configured to access the portion of the requested data within each of the plurality of ECC blocks and is configured to reconstruct the requested data.

25. An apparatus for reading data, the apparatus comprising:

means for receiving a read request from a requesting device for data stored on a solid-state storage device comprising two or more solid-state storage elements;

means for reading one or more error-correcting code (ECC) blocks comprising the requested data, each ECC block comprising at least a portion of the requested data and an error-correcting code capable of correcting an error in the portion of the requested data, wherein reading the one or more ECC blocks comprises reading, for a particular ECC block of the one or more ECC blocks, a first portion of the particular ECC block from a page of a first one of the solid-state storage elements and a second portion from a page of a second one of the solid-state storage elements;

means for correcting errors in the one or more ECC blocks in response to detecting the error; and

means for providing the requested data to the requesting device.