Method for manufacturing non-volatile magnetic memory

• US 8,535,952 B2
• Filed: 02/29/2008
• Issued: 09/17/2013
• Est. Priority Date: 02/25/2006
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: Ranjan, Rajiv Yadav, Keshtbod, Parviz, Malmhall, Roger Klas
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US12/040,827
• Publication Number:
  US 20080293165A1
• Time in Patent Office: 2,027 Days
• Field of Search: 438/3, 257/295, 257/E21.001, 257/E21.665, 257/E27.005
• US Class Current: 438/3
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.

Claims

1. A method of manufacturing a magnetic random access memory (MRAM) cell comprising:

a multi-stage manufacturing process including the steps of;

performing a front end on-line (FEOL) stage, in a first facility, to make logic and non-magnetic portions of a memory cell being manufactured including the steps of,

forming an intermediate interlayer dielectric (ILD) layer in the first facility;

forming intermediate metal pillars embedded in the intermediate ILD layer layer in the first facility; and

depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars to seal the intermediate ILD layer and the intermediate metal pillars and avoid oxidation of the intermediate metal pillars during transport, after the depositing step, a FEOL stage structure being formed;

transporting the FEOL stage structure from the first facility to a second facility before forming additional layers on top thereof;

performing magnetic fabrication stage, in a facility other than the first facility, to make a magnetic material portion of the memory cell being manufactured; and

performing back end on-line (BEOL) stage, in a facility other than the first facility, to make metal and contacts of the memory cell being manufactured.

2. A method of manufacturing, as recited in claim 1, wherein the FEOL stage further includes the steps of:

forming logic on top of a wafer, onto which memory cells are to be formed;

forming a first ILD layer on top of the logic; and

forming a plurality of first metal pillars dispersed in the first ILD layer.

3. A method of constructing a MRAM memory cell, as recited in claim 2, where the first metal pillars are made of tungsten.

4. A method of constructing a MRAM memory cell, as recited in claim 2, where the intermediate ILD layer is formed using a damascene process comprising:

forming a intermediate ILD layer on top of the first ILD layer and first metal pillars;

depositing photo resist on top of the intermediate ILD layer in a manner which covers substantially all of the ILD layer except the portion above the first metal pillars;

etching the intermediate ILD layer until the first metal pillars are exposed;

depositing a metal layer until the metal contacts the exposed, first metal pillars;

planerizing the metal leaving in place the second metal pillars.

5. A method of constructing a MRAM memory cell, as recited in claim 4, where the second metal pillars are formed from copper.

6. A method of constructing a MRAM memory cell, as recited in claim 4, where the intermediate ILD layer etching is done using reactive ion etching (RIE).

7. A method of constructing a MRAM memory cell, as recited in claim 2, where the intermediate ILD layer is formed using a non-damascene process comprising:

depositing a metal layer on top of the first ILD layer and first metal pillars;

depositing photo-resist pillars on top of the metal layer in a pattern substantially above the first metal pillars;

etching the metal layer until the second metal pillars remain;

depositing an ILD layer covering the entire wafer including the second metal pillars;

planerizing the ILD layer until the tops of the second metal pillars are exposed.

8. A method of constructing a MRAM memory cell, as recited in claim 2, where the second metal pillars are formed of copper.

9. A method of constructing a MRAM memory cell, as recited in claim 2, where the metal layer etching is done using reactive ion etching (RIE).

10. A method of constructing a MRAM memory cell, as recited in claim 2, where the first conductive metal cap is made of Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Chromium, Tungsten, Niobium or alloys containing one or more of these elements.

11. A method of manufacturing, as recited in claim 1, wherein the magnetic fabrication stage includes the steps of:

after the transporting step, depositing a magnetic tunneling junction (MTJ) film on top of the first conductive metal cap and a second conductive metal cap on top of the MTJ film;

depositing photo-resist pillars on top of the second conductive metal cap so that the photo-resist pillars are positioned substantially above the second metal pillars;

etching the second conductive metal cap and MTJ film but leaving an MTJ pillar;

forming a passivation cap over the remaining MTJ pillar and conductive metal pillar;

depositing photo-resist on the silicon nitride caps;

etching the first conductive metal cap to form the first conductive metal pillar and passivation cap;

depositing an ILD layer on top of the first conductive metal pillar, MTJ film, first conductive metal pillar, and passivation cap; and

planerizing the deposited ILD layer to expose the top of the second conductive metal pillar.

12. A method of constructing a MRAM memory cell, as recited in claim 11, wherein the passivation cap covers the MTJ and top-electrode.

13. A method of manufacturing, as recited in claim 12, wherein the passivation cap is made of a non-conductive material, and a temperature deposition of below approximately 350 degrees Celsius.

14. A method of manufacturing, as recited in claim 12, wherein the passivation cap is made of material from a group consisting of:

silicon nitride (Si3N4), silicon nitride (SiN), silicon oxy-nitride (SiON), zirconium oxide (ZrO2), zirconium nitride (ZrN), hafnium oxide (HfO2), hafnium nitride (HfN), tantalum nitride(TaN), titanium nitride(TiN), tantalum oxide(Ta2O5), aluminum oxide(Al2O3), or aluminum nitride(AlN).

15. A method of constructing a MRAM memory cell, as recited in claim 11, wherein the MTJ film is constructed using a cluster tool without breaking vacuum.

16. A method of constructing a MRAM memory cell, as recited in claim 11, where the second conductive metal cap is made of Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Chromium, Tungsten, Niobium or alloys containing one or more of these elements.

17. A method of constructing a MRAM memory cell, as recited in claim 11, where the second conductive metal cap is generally known as the top electrode.

18. A method of constructing a MRAM memory cell, as recited in claim 11, where the MTJ etching is done using reactive ion etching (RIE).

19. A method of constructing a MRAM memory cell, as recited in claim 11, where the MTJ etching is controlled using a hard mask.

20. A method of constructing a MRAM memory cell, as recited in claim 19, wherein the metal bars are formed using aluminum.

21. A method of constructing a MRAM memory cell, as recited in claim 19, wherein the metal bars are etched using reactive ion etching (RIE).

22. A method of manufacturing, as recited in claim 1, wherein the BEOL stage includes the steps of:

depositing a metal cap over the top of the wafer;

depositing photo resist over the top of the wafer;

etching the metal layers until only metal bars remain in a position substantially over the exposed second conductive metal pillars;

depositing a passivation layer over the top of the wafer to prevent electrical short circuit; and

depositing contact pads on top of the wafer.

23. A method of manufacturing a magnetic random access memory (MRAM) cell comprising:

a multi-stage manufacturing process including the steps of;

performing a front end on-line (FEOL) stage, in a first facility, to make logic and non-magnetic portions of a memory cell being manufactured including the steps of,

forming an intermediate interlayer dielectric (ILD) layer in the first facility;

forming intermediate metal pillars embedded in the intermediate ILD layer layer in the first facility; and

depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars to seal the intermediate ILD layer and the intermediate metal pillars and avoid oxidation of the intermediate metal pillars during transport, after the depositing step, a FEOL stage structure being formed;

transporting the FEOL stage structure from the first facility to a second facility before forming additional layers on top thereof;

performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured; and

performing back end on-line (BEOL) stage, in a facility other than the first facility, to make metal and contacts of the memory cell being manufactured.