Method for fabricating chip package with die and substrate

• US 8,535,976 B2
• Filed: 06/04/2003
• Issued: 09/17/2013
• Est. Priority Date: 12/31/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Lin, Mou-Shiung, Huang, Ching-Cheng
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US10/454,972
• Publication Number:
  US 20030205804A1
• Time in Patent Office: 3,758 Days
• Field of Search: 257/700, 257/773, 257/777, 257/782, 438/107, 438/108, 438110-113, 438/118, 438/125, 438/459
• US Class Current: 438/107
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Claims

1. A method for fabricating a chip package, comprising:

joining multiple dies, separated from one another, and a bottom surface of a first substrate;

after said joining said multiple dies and said bottom surface, thinning said first substrate; and

after said thinning said first substrate, forming a circuit layer on a top surface of said first substrate.

2. The method of claim 1, after said joining said multiple dies and said bottom surface, further comprising joining said multiple dies and a second substrate, followed by said thinning said first substrate.

3. The method of claim 1, after said joining said multiple dies and said bottom surface, further comprising thinning said multiple dies.

4. The method of claim 3, wherein said thinning said multiple dies comprises a grinding process.

5. The method of claim 1, after said joining said multiple dies and said bottom surface, further comprising forming a die-surrounding layer on said bottom surface and between said multiple dies.

6. The method of claim 5, wherein said die-surrounding layer comprises a polymer.

7. The method of claim 5, wherein said die-surrounding layer comprises an epoxy.

8. The method of claim 1 further comprising said thinning said first substrate to a thickness between 2 and 200 micrometers.

9. The method of claim 1, wherein said first substrate comprises a ceramic substrate.

10. The method of claim 1, wherein said first substrate comprises an organic substrate.

11. The method of claim 1, wherein said first substrate comprises a glass substrate.

12. The method of claim 1, wherein said forming said circuit layer comprises a sputtering process.

13. The method of claim 1, wherein said circuit layer comprises copper.

14. The method of claim 1, after said forming said circuit layer on said top surface, further comprising forming a dielectric layer on said circuit layer.

15. The method of claim 14, wherein said dielectric layer comprises polyimide.

16. The method of claim 14, wherein said dielectric layer comprises benzocyclobutene.

17. The method of claim 1, wherein said circuit layer comprises a ground bus.

18. The method of claim 1, wherein said circuit layer comprises an interconnect connecting multiple portions of one of said multiple dies.

19. The method of claim 1, wherein said circuit layer comprises a power bus.

20. The method of claim 1, wherein said circuit layer comprises an interconnect connecting said multiple dies.

21. The method of claim 1, wherein one of said multiple dies comprises multiple active devices, and said circuit layer comprises an interconnect connecting said multiple active devices.

22. The method of claim 1 further comprising cutting said first substrate into multiple portions.

23. The method of claim 22, wherein after said cutting said first substrate into said multiple portions, only one die, one of said multiple dies, joins one of said multiple portions.

24. The method of claim 22, wherein after said cutting said first substrate into said multiple portions, said multiple dies join one of said multiple portions.

25. The method of claim 2, wherein said second substrate comprises a ceramic substrate.

26. The method of claim 5, wherein said die-surrounding layer comprises an oxide.

27. The method of claim 1, wherein said forming said circuit layer comprises an electroless plating process.

28. The method of claim 1, wherein said forming said circuit layer comprises an electroplating process.

29. A method for fabricating a chip package, comprising:

forming a polymer structure covering a die, wherein said die is between a first portion of said polymer structure and a second portion of said polymer structure, wherein a third portion of said polymer structure covers a top surface of said die;

after said forming said polymer structure, thinning said die and then forming a patterned circuit layer over said die and said polymer structure, wherein said patterned circuit layer extends across an edge of said die, wherein said patterned circuit layer comprises a portion of an inductor;

forming a dielectric layer on said patterned circuit layer and over said die and said polymer structure; and

after said forming said dielectric layer, cutting said polymer structure.

30. The method of claim 29, after said forming said dielectric layer, further comprising forming a solder bump vertically over said polymer structure, followed by said cutting said polymer structure.

31. The method of claim 29, wherein said forming said patterned circuit layer comprises an electroplating process.

32. The method of claim 29, wherein said forming said patterned circuit layer comprises a sputtering process.

33. The method of claim 29, wherein said polymer structure comprises an epoxy.

34. The method of claim 29, after said forming said dielectric layer, further comprising forming a gold bump vertically over said polymer structure, followed by said cutting said polymer structure.

35. The method of claim 29 further comprising joining said die and a substrate, followed by said forming said polymer structure.

36. A method for fabricating a chip package, comprising:

joining multiple dies, separated from one another, and a substrate;

after said joining said multiple dies and said substrate, thinning said substrate; and

after said joining said multiple dies and said substrate, forming multiple openings in said substrate.

37. The method of claim 36, wherein said thinning said substrate is followed by said forming said multiple openings.

38. The method of claim 36, wherein said forming said multiple openings comprises an etching process.

39. The method of claim 36, wherein said forming said multiple openings comprises a drilling process.

40. The method of claim 36, after said forming said multiple openings in said substrate, further comprising forming a circuit layer on said substrate, wherein said circuit layer is connected to said multiple dies through said multiple openings.

41. The method of claim 36, after said forming said multiple openings in said substrate, further comprising cutting said substrate into multiple portions.

42. The method of claim 41, wherein after said cutting said substrate into said multiple portions, only one die, one of said multiple dies, joins one of said multiple portions.

43. The method of claim 41, wherein after said cutting said substrate into said multiple portions, said multiple dies join one of said multiple portions.