Large panel leadframe

• US 8,535,988 B2
• Filed: 05/25/2012
• Issued: 09/17/2013
• Est. Priority Date: 11/01/2011
• Status: Expired due to Fees

• Current Assignee: Carsem (M) SDN BHD (Hong Leong Company (Malaysia) Bhd.)
• Original Assignee: Carsem (M) SDN BHD (Hong Leong Company (Malaysia) Bhd.)
• Inventors: Wai, Yong Lam, Meng, Chan Boon, Keat, Phang Hon
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US13/481,652
• Publication Number:
  US 20130109137A1
• Time in Patent Office: 480 Days
• Field of Search: 438/110, 438/122, 438/123, 257/676
• US Class Current: 438/123
• CPC Class Codes: B29C 2043/3433 using dispensing heads, e.g. extruders, placed over or apart from the moulds
• CPC Class Codes: B29C 43/021 characterised by the shape of the surface
• CPC Class Codes: B29C 43/18 incorporating preformed parts or layers, e.g. compression moulding around inserts or for coating articles B29C43/206 takes precedence
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/32257 the layer connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85013 Plasma cleaning
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2933/005 : relating to encapsulations
• CPC Class Codes: H01L 33/54 : having a particular shape

Abstract

A method of manufacturing an integrated circuit package includes mounting a large panel leadframe having a substantially square shape to a ring. The large panel leadframe includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. An integrated circuit chip is attached to each of the die pads. An encapsulant material is applied over the integrated circuit chips and at least a part of the large panel leadframe. Each of the die pads and its corresponding leads are separated from the large panel leadframe to form individual integrated circuit packages. The steps of attaching the integrated circuit chips and applying the encapsulant material are performed while the large panel leadframe is mounted to a taped ring.

Claims

1. A method of manufacturing integrated circuit packages, the method comprising:

mounting a large panel leadframe having a substantially square shape to a ring, wherein the large panel leadframe includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern;

attaching an integrated circuit chip to each of the die pads;

applying an encapsulant material over the integrated circuit chips and at least a portion of the large panel leadframe; and

separating the plurality of die pads and the corresponding leads from the large panel leadframe to form the integrated circuit packages, wherein the steps of attaching the integrated circuit chips and applying the encapsulant material are performed while the large panel leadframe is mounted to the ring.

2. The method of claim 1 wherein applying the encapsulant further comprises;

providing an array mold cavity;

dispensing the encapsulant material into the array mold cavity;

engaging the array mold cavity including the encapsulant material with the large panel leadframe including the integrated circuit chips; and

curing the encapsulant material.

3. The method of claim 1 wherein the large panel leadframe is mounted to the ring using an adhesive tape.

4. The method of claim 1 wherein the large panel leadframe and ring are transported using a handler that provides movement in forward/backward and lateral directions during the steps of attaching the integrated circuit chips, applying the encapsulant material, and separating the plurality of die pads and the corresponding leads from the large panel leadframe.

5. The method of claim 1 wherein each of the plurality of die pads are planar.

6. The method of claim 1 wherein each of the plurality of die pads include a planar surface extending along a bottom of a recessed cavity.

7. The method of claim 1 wherein the large panel leadframe has a size of about 200 mm by about 200 mm.

8. The method of claim 1 wherein the integrated circuit chips are attached to each of the plurality of die pads using an epoxy.

9. The method of claim 1 further comprising wirebonding the plurality of leads of the large panel leadframe to respective bonding pads disposed on a surface of the integrated circuit chips.

10. The method of claim 1 wherein the ring is substantially planar and the large panel leadframe is mounted to a surface of the ring.

11. The method of claim 1 wherein the integrated circuit chips include at least one of a light emitting diode (LED), a memory device, a logic device, or a processor.

12. The method of claim 1 wherein the integrated circuit packages include at least one of a quad-flat no-leads (QFN) package, a ball grid array (BGA) package, a small scale ball grid array (SSBGA) package, a land grid array (LGA) package, a system-in-package (SiP) package, or a mini-pak package.

13. A method of manufacturing integrated circuit packages, the method comprising:

mounting a large panel leadframe to a ring, wherein the large panel leadframe includes a plurality of die pads and a corresponding plurality of leads surrounding the die pads, the plurality of die pads and the plurality of leads arranged in a matrix pattern;

attaching an integrated circuit chip to each of the plurality of die pads;

wirebonding each of the plurality of leads to respective bonding pads disposed on a surface of the integrated circuit chips;

applying an encapsulant material overlaying the integrated circuit chips and at least a part of the large panel leadframe; and

separating the plurality of die pads and the corresponding leads from the large panel leadframe to form the integrated circuit packages, wherein the steps of attaching the integrated circuit chips, wirebonding each of the plurality of leads, applying the encapsulant material, and separating the plurality of die pads are performed while the large panel leadframe is mounted to the ring.

14. The method of claim 13 wherein each of the plurality of die pads are planar.

15. The method of claim 13 wherein each of the plurality of die pads include a planar surface extending along a bottom of a recessed cavity.

16. The method of claim 13 wherein the integrated circuit chips include at least one of a light emitting diode (LED), a memory device, a logic device, or a processor.

17. The method of claim 13 wherein the ring is substantially planar and the large panel leadframe is mounted to a surface of the ring.

18. A method of manufacturing integrated circuit packages, the method comprising:

mounting a large panel leadframe to a ring, wherein the large panel leadframe includes a plurality of die attach regions and a corresponding plurality of leads surrounding the die attach regions, the plurality of die attach regions and the plurality of leads arranged in a matrix pattern;

placing one or more integrated circuit chips in each of the plurality of die attach regions;

wirebonding each of the plurality of leads to respective bonding pads disposed on a surface of the integrated circuit chips;

applying an encapsulant material overlaying the integrated circuit chips and at least a part of the large panel leadframe; and

separating the plurality of die attach regions and the corresponding leads from the large panel leadframe to form the integrated circuit packages, wherein the steps of placing one or more circuit chips in each of the die attach regions, wirebonding each of the plurality of leads to respective bonding pads, applying the encapsulant material, and separating the plurality of die attach regions and corresponding leads from the large panel leadframe may be performed while the large panel leadframe is mounted to the ring.

19. The method of claim 18 wherein the die attach regions include die pads.

20. The method of claim 18 wherein the die attach regions do not include die pads.