Thyristor random access memory device and method

• US 8,535,992 B2
• Filed: 06/29/2010
• Issued: 09/17/2013
• Est. Priority Date: 06/29/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Zahurak, John K., Violette, Michael P.
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Parker, John M
• Application Number:
  US12/826,323
• Publication Number:
  US 20110316042A1
• Time in Patent Office: 1,176 Days
• Field of Search: 438/128, 438/133, 438/292, 438/295, 438/296, 438/115, 257/107, 257/300, 257/301, 257/302, 257/E27.075
• US Class Current: 438/133
• CPC Class Codes: H01L 27/1027 Thyristors
• CPC Class Codes: H01L 29/42308 Gate electrodes for thyristors
• CPC Class Codes: H01L 29/66363 Thyristors
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 2924/1301 Thyristor

Abstract

Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

Claims

1. A method comprising:

forming a channel in a first type semiconductor portion to form a “

U”

shaped portion;

forming a dielectric material within the channel;

forming a control line over the dielectric material;

implanting a second type dopant into both top portions of the “

U”

shaped portion to form a pair of implanted regions above the control line; and

forming an upper first type semiconductor portion over one of the implanted regions.

2. The method of claim 1, wherein the first type semiconductor portion is P-doped and the second type dopant is an N-type dopant.

3. The method of claim 2, wherein implanting a second type dopant into both top portions of the “

U”

shaped portion includes heavily doping (N+) into at least one top portion of the “

U”

shaped portion.

4. The method of claim 3, wherein forming an upper first type semiconductor portion over one of the implanted regions includes forming a heavily doped (P+) portion over one of the implanted regions.

5. The method of claim 1, further including forming a first transmission line coupled to a second of the pair of implanted regions.

6. The method of claim 5, further including forming a second transmission line coupled to the upper first type semiconductor portion.

7. The method of claim 6, wherein the first and second transmission lines are formed substantially orthogonal.

8. The method of claim 6, wherein forming a second transmission line includes forming a first type semiconductor material and forming a metal cap material over the first type semiconductor material.

9. The method of claim 8, wherein forming the first type semiconductor material includes forming a heavily doped (P+) material.

10. A method comprising:

forming a conductor region beneath a first type semiconductor portion separated therefrom by a dielectric material;

forming a channel in the first type semiconductor portion to form a “

U”

shaped portion;

forming a dielectric material within the channel;

forming a control line over the dielectric material;

implanting a second type dopant into both top portions of the “

U”

shaped portion to form a pair implanted regions; and

forming an upper first type semiconductor portion over one of the implanted regions.

11. The method of claim 10, wherein forming a conductor region includes forming a metal region.

12. The method of claim 10, wherein forming the conductor region beneath the first type semiconductor portion separated therefrom by a dielectric material includes:

forming a dielectric material over a first type semiconductor substrate;

forming a conductor region over the dielectric material; and

flipping and bonding the conductor region to a second substrate.

13. The method of claim 12, wherein forming the conductor region beneath the first type semiconductor portion further includes thinning the flipped first type semiconductor substrate using an implanted marker.

14. The method of claim 12, wherein flipping and bonding the conductor region to a second substrate includes flipping and bonding the conductor region to an oxidized surface material of a silicon substrate.

15. The method of claim 12, wherein flipping and bonding the conductor region to a second substrate includes forming an amorphous silicon material over the conductor region, and flipping and bonding the amorphous silicon material to an oxidized surface material of a silicon substrate.