Stress memorization process improvement for improved technology performance

• US 8,535,999 B2
• Filed: 10/12/2010
• Issued: 09/17/2013
• Est. Priority Date: 10/12/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Mehta, Sanjay, Zhu, Zhengmao, Adam, Lahir
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US12/902,624
• Publication Number:
  US 20120086071A1
• Time in Patent Office: 1,071 Days
• Field of Search: 438197-199, 438299-308, 438/761, 438/783, 257/E21.473, 257632-635, 257/29.345
• US Class Current: 438/199
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.

Claims

1. A method of fabricating a semiconductor structure, comprising:

providing a semiconductor substrate;

forming a gate structure on the semiconductor substrate by forming a polycrystalline gate material in direct contact with the semiconductor substrate;

forming a source-drain implant region adjacent to the gate structure and in direct contact with both the polycrystalline gate material and the semiconductor substrate;

forming a compressive stress-transmitting dielectric layer on the source-drain implant region and the gate structure and permanently deforming an underlying channel region located between the source and drain regions and below the polycrystalline gate material by elongating the channel region perpendicular to the semiconductor substrate;

removing the stress-transmitting dielectric layer; and

performing an annealing step after the removing of the stress-transmitting dielectric layer.

2. The method of claim 1, further comprising transferring a uniaxial compressive stress from the stress-transmitting dielectric layer to the gate structure.

3. The method of claim 2, wherein the uniaxial compressive stress in the gate structure is of from about 300 MPa to about 3 GPa.

4. The method of claim 1, wherein annealing step is effected at a temperature of from about 950°

C. to about 1,200°

C.

5. The method of claim 1, wherein the stress-transmitting dielectric layer is a refractory metal nitride.

6. The method of claim 5, wherein the refractory metal nitride is selected from the group consisting of TaN, TiN, WN, MoN, NbN, ReN, and a combination thereof.

7. The method of claim 6, wherein the refractory metal nitride is TiN.

8. The method of claim 1, further comprising applying a capping layer on the source-drain implant region prior to the forming of the stress-transmitting dielectric layer.

9. The method of claim 1, wherein the stress-transmitting dielectric layer is a silicon oxide.

10. The method of claim 1, wherein the stress-transmitting dielectric layer exerts a pressure of from about 300 MPa to about 3 GPa.

11. The method according to claim 1, wherein the semiconductor structure is a n-type metal-oxide-semiconductor (NMOS).

12. The method according to claim 1, wherein the semiconductor structure is a p-type metal-oxide-semiconductor (PMOS).

13. The method according to claim 1, wherein both the source region and the drain region are doped.

14. The method according to claim 1, wherein the method further comprises forming a gate spacer adjacent to and in direct contact with the polycrystalline gate material.

15. The method according to claim 14, wherein the method further comprises forming an extension spacer adjacent to and in direct contact with the gate spacer.

16. The method according to claim 15, wherein the gate spacer comprises a nitride layer on a liner oxide layer.