Method of manufacturing a semiconductor device and structure

• US 8,536,023 B2
• Filed: 11/22/2010
• Issued: 09/17/2013
• Est. Priority Date: 11/22/2010
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Primary Examiner(s): SANDVIK, BENJAMIN P
• Application Number:
  US12/951,913
• Publication Number:
  US 20120220102A1
• Time in Patent Office: 1,030 Days
• Field of Search: None
• US Class Current: 438/458
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/13062 Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

A method of manufacturing semiconductor wafers, the method including: providing a donor wafer including a semiconductor substrate; performing a lithography step and processing the donor wafer; and performing at least two subsequent steps of layer transfer out of the donor wafer, each layer transfer step producing a transferred layer, where each of the transferred layers had been affected by the lithography step, and where each of the transferred layer includes a plurality of transistors with side gates, and where the layer transfer includes an ion-cut, the ion-cut including an ion implant thru the transistors.

Claims

1. A method of manufacturing semiconductor wafers, the method comprising:

providing a donor wafer comprising a semiconductor substrate;

performing a lithography step and processing the donor wafer; and

performing at least two subsequent steps of layer transfer out of said donor wafer, each said step producing a transferred layer,

wherein each of said transferred layer had been affected by said lithography step, and

wherein each of said transferred layer comprises a plurality of transistors with side gates, and

wherein said layer transfer comprises an ion-cut, said ion-cut comprising an ion implant thru said transistors.

2. A method according to claim 1, comprising a follow on processing to finish processing at least two acceptor wafers wherein each of said at least two acceptor wafers comprise one of said transferred layer.

3. A method according to claim 1, comprising a follow on processing to finish processing one wafer comprising at least two of said transferred layer.

4. A method according to claim 1, wherein said plurality of transistors comprise junctionless transistors.

5. A method according to claim 1, wherein said plurality of transistors comprise Finfet transistors.

6. A method according to claim 1, wherein said plurality of transistors comprise transistors constructed with replacement gate processes.

7. A method according to claim 1, wherein each of said transferred layer are used to form logic circuits.

8. A method according to claim 1, wherein each of said transferred layer are used to form memory circuits.

9. A method according to claim 1, wherein each of said transferred layer are constructed from a mono-crystallized layer.

10. A method of manufacturing semiconductor wafers, the method comprising:

providing a first wafer comprising a semiconductor substrate;

performing a lithography step and processing said first wafer accordingly; and

then

completing the subsequent fabrication of at least a second wafer and a third wafer with distinct steps,

wherein each of said at least a second wafer and a third wafer utilized said lithography step, and

wherein each of said at least a second wafer and a third wafer comprises a plurality of transistors with side gates, and

wherein said distinct steps comprise an ion-cut, said ion-cut comprising an ion implant thru said transistors.

11. A method according to claim 10, comprising a layer transfer from said wafer to each of said at least a second wafer and a third wafer.

12. A method according to claim 10, comprising a follow on processing to finish processing of the interconnection of said transistors of said at least a second wafer and a third wafer wherein each of said at least a second wafer and a third wafer comprise material from said first wafer.

13. A method according to claim 10, wherein said plurality of transistors comprise junction-less-transistors.

14. A method according to claim 10, wherein said plurality of transistors comprise Finfet transistors.

15. A method according to claim 10, wherein said plurality of transistors comprise transistors constructed with replacement gate processes.

16. A method according to claim 10, wherein said at least a second wafer and a third wafer comprise logic circuits.

17. A method according to claim 10, wherein said at least a second wafer and a third wafer comprise memory circuits.

18. A method according to claim 10, wherein said at least a second wafer and a third wafer are constructed from mono-crystallized layers.

19. A method of manufacturing semiconductor wafers, the method comprising:

providing a first wafer comprising a semiconductor substrate;

performing a lithography step and processing said first wafer accordingly; and

then

completing subsequently a wafer fabrication providing at least a first layer and a second layer,

wherein each of said first layer and said second layer comprises a portion of said first wafer, and

wherein each of said first layer and said second layer comprises transistors of mono-crystallized material, said transistors with side gates, and

wherein each of said first layer and said second layer had been affected by said lithography step, and

wherein said wafer fabrication comprises an ion-cut, said ion-cut comprising an ion implant thru said transistors.

20. A method according to claim 19, comprising a follow on processing to finish processing at least a second wafer and a third wafer, wherein each of said second wafer and third wafer comprise one of said first layer or said second layer.

21. A method according to claim 19, comprising a follow on processing to finish processing a fourth wafer comprising said first layer and said second layer.

22. A method according to claim 19, wherein said transistors comprise junction-less-transistors.

23. A method according to claim 19, wherein said transistors comprise Finfet transistors.

24. A method according to claim 19, wherein said transistors comprise transistors constructed with replacement gate processes.

25. A method according to claim 19, wherein said first layer and said second layer are used to form logic circuits.

26. A method according to claim 19, wherein said first layer and said second layer are used to form memory circuits.

27. A method according to claim 19, wherein said first layer and said second layer had been processed with a layer transfer process.

28. A method of manufacturing semiconductor wafers, the method comprising:

providing a base wafer;

performing a first and then subsequently a second layer transfer of a first layer and a second layer onto said base wafer; and

then

performing a lithography step and processing said first layer and said second layer according to said lithography step; and

then

performing a third layer transfer of said first layer and said second layer,

wherein said first layer and said second layer comprise substantially the same material, and

wherein each of said first layer and said second layer comprises a plurality of transistors with side gates, and

wherein said third layer transfer comprises an ion-cut, said ion-cut comprising an ion implant thru said transistors.

29. A method according to claim 28 wherein said transistors comprise mono-crystallized material.

30. A method according to claim 28, comprising a follow on processing to finish processing at least a first wafer and a second wafer wherein said first wafer comprises said first layer and said second wafer comprises said second layer.

31. A method according to claim 28, comprising a follow on processing to finish processing a first wafer comprising said first layer and said second layer.

32. A method according to claim 28, wherein said transistors comprise junction-less-transistors.

33. A method according to claim 28, wherein said transistors comprise Finfet transistors.

34. A method according to claim 28, wherein said transistors comprise transistors constructed with replacement gate processes.

35. A method according to claim 28, wherein said first layer and said second layer are used to form logic circuits.

36. A method according to claim 28, wherein said first layer and said second layer are used to form memory circuits.

37. A method according to claim 28, wherein said first layer transfer and said second layer transfer each comprise an ion implant step.

38. A method of manufacturing semiconductor wafers, the method comprising:

providing a donor wafer comprising a semiconductor substrate;

performing a lithography step and processing said donor wafer accordingly; and

then

performing a first layer transfer to a carrier wafer and subsequently performing at least a second step and a third step of layer transfer out of said carrier wafer forming at least two transferred layers,

wherein each of said at least two transferred layers had been affected by said lithography step, and

wherein each of said at least two transferred layers comprise a plurality of transistors with side gates, and

wherein said second step and said third step of layer transfer each comprise an ion-cut, said ion-cut comprising an ion implant thru said transistors.

39. A method according to claim 38, comprising a follow on processing to finish processing at least a first wafer and a second wafer wherein each of said first wafer and said second wafer comprise one of said at least two transferred layers.

40. A method according to claim 38, comprising a follow on processing to finish processing a first wafer comprising two of said at least two transferred layers.

41. A method according to claim 38, wherein said two transferred layers comprise junction-less-transistors.

42. A method according to claim 38, wherein said two transferred layers comprise Finfet transistors.

43. A method according to claim 38, wherein said two transferred layers comprise transistors constructed with replacement gate processes.

44. A method according to claim 38, wherein said two transferred layers are used to form logic circuits.

45. A method according to claim 38, wherein said two transferred layers are used to form memory circuits.

46. A method according to claim 38, wherein said two transferred layers are constructed from a mono-crystallized layer.

47. A method according to claim 38, wherein said first layer transfer comprises an ion implant step.

48. A method according to claim 38, wherein each of said at least two transferred layers had been affected by said processing.