Method of forming a topside contact to a backside terminal of a semiconductor device

• US 8,536,042 B2
• Filed: 12/30/2010
• Issued: 09/17/2013
• Est. Priority Date: 10/02/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Andrews, John T., Yilmaz, Hamza, Marchant, Bruce, Ho, Ihsiu
• Primary Examiner(s): Sefefr, A.
• Assistant Examiner(s): KHAN, FARID H
• Application Number:
  US12/982,509
• Publication Number:
  US 20110097894A1
• Time in Patent Office: 992 Days
• Field of Search: 438/233, 438/399, 438/597, 438/618, 438/620, 438/621, 257/263, 257/278, 257/302, 257/328, 257/329, 257/330, 257/342, 257/418, 257/E29.201, 257/E29.257, 257/E29.261, 257/E29.267, 257/E21.375, 257/E21.376, 257/E21.377, 257/E21.383
• US Class Current: 438/597
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

Claims

1. A method of forming a semiconductor device comprising:

forming an epitaxial layer on a topside surface of a semiconductor substrate, a sidewall of the epitaxial layer defining a recessed region along a periphery of the semiconductor device;

forming a highly doped implant region in the sidewall of the epitaxial layer and an upper portion of the recessed region;

forming an active device structure in an active area of the epitaxial layer;

forming a termination region in the epitaxial layer, the termination region being disposed between the active area and the recessed region; and

forming an interconnect layer disposed on at least a portion of the termination region, at least a portion of the sidewall of the epitaxial layer, and at least a portion of the recessed region, the interconnect layer being configured as a topside contact to the semiconductor substrate.

2. The method of claim 1, wherein forming the epitaxial layer includes performing a selective epitaxial growth process.

3. The method of claim 1, wherein forming the termination region includes forming one or more active area termination structures.

4. The method of claim 1, wherein forming the termination region includes forming at least one of a field oxide region in the epitaxial layer or a dielectric layer disposed on the epitaxial layer.

5. The method of claim 1, wherein the recessed region is configured as a drain terminal of the semiconductor device, and the forming the active device structure in the active area includes:

forming a gate of the semiconductor device; and

forming a source terminal of the semiconductor device.

6. The method of claim 1, wherein the termination region surrounds the active area.

7. The method of claim 1, wherein the recessed region is configured to provide an equal potential ring around the active area.

8. The method of claim 1, wherein the sidewall of the epitaxial layer has a slope between 45 degrees and 90 degrees.

9. The method of claim 1, further comprising forming a conductive layer on a backside surface of the semiconductor substrate.

10. The method of claim 1, wherein the recessed region is defined using an etch process to remove a portion of the epitaxial layer, the etch process forming the sidewall of the epitaxial layer.

11. A method of forming a semiconductor device comprising:

forming an epitaxial layer on a topside surface of a semiconductor substrate, a sidewall of the epitaxial layer defining a recessed region along a periphery of the semiconductor device, the epitaxial layer including a notched active area;

forming a highly doped implant region in the sidewall of the epitaxial layer and in an upper portion of the recessed region;

forming a termination region in the epitaxial layer, the termination region being disposed around a perimeter of the notched active area; and

forming an interconnect layer disposed on at least a portion of the termination region;

at least a portion of the sidewall of the epitaxial layer and at least a portion of the recessed region, the interconnect layer being configured to function as a topside contact to the semiconductor substrate.

12. The method of claim 11, further comprising forming an active device structure in the notched active area, the active device structure including a gate of the semiconductor device and a source terminal of the semiconductor device, the recessed region functioning as a drain terminal of the semiconductor device.

13. The method of claim 11, wherein the recessed region forms an equal potential ring around the termination region.

14. The method of claim 11, wherein forming the termination region includes forming at least one of a field oxide region in the epitaxial layer or a dielectric layer disposed on the epitaxial layer.

15. The method of claim 11, wherein the sidewall of the epitaxial layer has a slope between 45 degrees and 90 degrees.

16. A method of forming a semiconductor device comprising:

forming an epitaxial layer on a topside surface of a semiconductor substrate, a sidewall of the epitaxial layer defining a recessed region along a periphery of the semiconductor device;

forming a highly doped implant region in the sidewall of the epitaxial layer and in an upper portion of the recessed region;

forming an active device structure in an active area of the epitaxial layer;

forming a termination region in the epitaxial layer, the termination region being disposed between the active area and the recessed region around a perimeter of the active area; and

forming an interconnect layer disposed on at least a portion of the termination region, at least a portion of the sidewall of the epitaxial layer, and at least a portion of the recessed region, the interconnect layer being configured to function as a topside contact to the semiconductor substrate.

17. The method of claim 16, wherein forming the termination region includes forming one or more termination structures.

18. The method of claim 16, wherein the recessed region is configured as a drain terminal of the semiconductor device, and the forming the active device structure in the active area includes:

forming a gate of the semiconductor device; and

forming a source terminal of the semiconductor device.