Digitally controlled oscillator with thermometer sigma delta encoded frequency control word

• US 8,536,916 B1
• Filed: 09/12/2012
• Issued: 09/17/2013
• Est. Priority Date: 09/12/2011
• Status: Active Grant

• Current Assignee: MaxLinear Communications, LLC (f/k/a Entropic Communications, LLC) (Maxlinear Incorporated)
• Original Assignee: Entropic Communications Incorporated (Maxlinear Incorporated)
• Inventors: van Engelen, Josephus A., Baumer, Howard A., Yu, Hairong
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/612,613
• Time in Patent Office: 370 Days
• Field of Search: 327/148, 327/159
• US Class Current: 327/159
• CPC Class Codes: H03L 1/022 by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature H03L1/021 takes precedence
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digital phase locked loop for generating an output clock signal includes a thermometer pulse coder configured to generate a frequency control word (FCW) that includes thermometer coded signals and a pulse modulated dither signal, and transmit the pulse modulated dither signal over a selected FCW signal line and transmit the thermometer coded signals over other FCW signal lines, and a digitally controlled oscillator to receive a FCW comprising a combined thermometer and pulse modulated signal and generate an output clock signal.

Claims

1. An all digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal, the ADPLL comprising:

a thermometer pulse coder including a plurality of frequency control word signal lines, where the thermometer pulse coder is configured to;

generate a frequency control word from a binary encoded frequency control word, where the frequency control word includes a plurality of thermometer coded signals and a pulse modulated dither signal; and

select one of the plurality of frequency control word signal lines and transmit the pulse modulated dither signal over the selected frequency control word signal line and transmit the thermometer coded signals over a plurality of the other frequency control word signal lines;

a digitally controlled oscillator configured to receive a frequency control word comprising a combined thermometer and pulse modulated signal via the plurality of frequency control world signal lines and generate an output clock signal at a frequency determined using at least the frequency control word;

a feedback divider configured to receive the output clock signal from the digitally controlled oscillator and generate a feedback signal; and

a phase detector configured to receive a reference clock signal and a feedback signal from the feedback divider and generate a phase error signal, which is provided to a digital loop filter configured to generate a binary encoded frequency control word that is input to the thermometer pulse coder.

2. The phase locked loop of claim 1, wherein the thermometer pulse coder further comprises a thermometer coder configured to generate a plurality of thermometer coded signals and a pulse modulation coder configured to generate a pulse modulated dither signal.

3. The phase locked loop of claim 2, wherein the pulse modulation coder is configured to generate a sigma delta coded dither signal using sigma delta coding.

4. The phase locked loop of claim 2, wherein the thermometer pulse coder further comprises a plurality of line encoders configured to:

receive at least two of the plurality of thermometer coded signals and the pulse modulated dither signal;

determine, based upon the values on the received thermometer coded signals, whether to output one of the received thermometer coded signals or the received pulse modulated dither signal.

5. The phase locked loop of claim 4, wherein at least one of the line encoders comprises:

an AND gate that receives a first of the plurality of thermometer coded signals and a second of the plurality of thermometer coded signals; and

a MUX that receives the output of the AND gate, the first of the plurality of thermometer coded signals, and the pulse modulated dither signal, and is configured to output either the first of the plurality of thermometer coded signals or the pulse modulated dither signal based upon the output of the AND gate.

6. The phase locked loop of claim 1, wherein the phase detector is a bang-bang phase detector.

7. The phase locked loop of claim 1, further comprising a prescaler configured to receive the output clock signal from the digitally controlled oscillator and scale the frequency of the output clock signal.

8. The phase locked loop of claim 7, wherein the feedback divider is a programmable integer N feedback divider.

9. The phase locked loop of claim 8, wherein the received reference clock signal is 25 Hz, the digitally controlled oscillator produces an output frequency 240 times greater than the reference clock signal, the prescaler divides the output clock signal frequency by two, and the feedback divider multiplies the received output clock signal by 2/240.

10. The phase locked loop of claim 1 wherein the digital loop filter comprises:

an integral phase error path that is configured to receive the phase error from the phase detector and has an adjustable gain; and

a frequency error path that is configured to receive the reference clock signal and a signal from the feedback divider and has an adjustable gain.

11. The phase locked loop of claim 1, further comprising a state machine configured to control zone frequency tuning.

12. The phase locked loop of claim 1, wherein the digitally controlled oscillator is an inductor-capacitor oscillator.

13. The phase locked loop of claim 1, wherein the digitally controlled oscillator comprises a zone capacitor array, a fine frequency tuning capacitor array, and a proportional tuning capacitor array.

14. The phase locked loop of claim 13, wherein the zone capacitor array comprises metal-to-metal capacitors.

15. The phase locked loop of claim 13, wherein the fine frequency tuning capacitor array comprises NMOS varactors.

16. The phase locked loop of claim 13, wherein the proportional tuning capacitor array comprises metal-to-metal capacitors and binary weighted NMOS varactors.

17. The phase locked loop of claim 13, wherein the digitally controlled oscillator further comprises a proportional-to-absolute-temperature circuit.