Multi-stage impedance matching

• US 8,536,950 B2
• Filed: 12/17/2009
• Issued: 09/17/2013
• Est. Priority Date: 08/03/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Nejati, Babak, Zhao, Yu, Pletcher, Nathan M, Hadjichristos, Aristotele, See, Puay Hoe
• Primary Examiner(s): Choe, Henry
• Application Number:
  US12/641,228
• Publication Number:
  US 20110037516A1
• Time in Patent Office: 1,370 Days
• Field of Search: 330/302, 330/51, 330/124.R, 330/295
• US Class Current: 330/302
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

Exemplary techniques for performing impedance matching are described. In an exemplary embodiment, the apparatus may include an amplifier (e.g., a power amplifier) coupled to first and second matching circuits. The first matching circuit may include multiple stages coupled to a first node and may provide input impedance matching for the amplifier. The second matching circuit may include multiple stages coupled to a second node and may provide output impedance matching for the amplifier. At least one switch may be coupled between the first and second nodes and may bypass or select the amplifier. The first and second nodes may have a common impedance. The apparatus may further include a second amplifier coupled in parallel with the amplifier and further to the matching circuits. The second matching circuit may include a first input stage coupled to the amplifier, a second input stage coupled to the second amplifier, and a second stage coupled to the two input stages via switches.

Claims

1. An apparatus comprising:

a first matching circuit comprising multiple stages configured for selectively coupling in series;

a second matching circuit comprising multiple stages configured for selectively coupling in series;

an amplifier coupled to the first and second matching circuits, the first matching circuit provides input impedance matching for the amplifier, and the second matching circuit provides output impedance matching for the amplifier; and

a selectable signal path from within the first matching circuit to within the second matching circuit that bypasses the amplifier.

2. The apparatus of claim 1, the first matching circuit comprises first and second stages coupled to a first node, and the second matching circuit comprises first and second stages coupled to a second node.

3. The apparatus of claim 2, further comprising:

at least one switch coupled between the first and second nodes and to bypass or select the amplifier.

4. The apparatus of claim 2, the first node has a first impedance and the second node has a second impedance matching the first impedance.

5. The apparatus of claim 2, the first node has a first impedance and the second node has a second impedance different from the first impedance.

6. The apparatus of claim 1, further comprising:

a second amplifier coupled in parallel with the amplifier and further to the first and second matching circuits.

7. The apparatus of claim 6, the second matching circuit comprising

a first input stage coupled to the amplifier,

a second input stage coupled to the second amplifier, and

a second stage coupled to the first and second input stages via switches.

8. The apparatus of claim 7, the first and second input stages each has a target output impedance when not coupled to the second stage, and the second stage has the target output impedance when coupled to the first and second input stages.

9. The apparatus of claim 7, the first input stage provides a first output radio frequency (RF) signal in a first mode, the second input stage provides a second output RF signal in a second mode, and the second stage provides a third output RF signal in a third mode.

10. The apparatus of claim 7, the first matching circuit comprises first and second stages coupled to a first node, the apparatus further comprising:

at least one switch coupled between the first node and the second stage of the second matching circuit, the first stage of the first matching circuit has an output impedance of one half the target output impedance, and the second stage of the second matching circuit has an input impedance of one half the target output impedance.

11. The apparatus of claim 1, the amplifier comprises a power amplifier.

12. The apparatus of claim 11, further comprising:

a driver amplifier coupled to the first matching circuit, the first matching circuit provides output impedance matching for the driver amplifier; and

a third matching circuit coupled to the driver amplifier, the third matching circuit provides input impedance matching for the driver amplifier.

13. The apparatus of claim 12, further comprising:

at least one switch to bypass or select the driver amplifier and the power amplifier.

14. The apparatus of claim 13, the at least one switch is coupled between the third matching circuit and a node between two stages in the second matching circuit, at least one stage in the second matching circuit provides filtering when the driver amplifier and the power amplifier are bypassed.

15. The apparatus of claim 2, the first matching circuit comprises a highpass network for the first stage and a lowpass network for the second stage.

16. The apparatus of claim 2, the second matching circuit comprises a first lowpass network for the first stage and a second lowpass network for the second stage.

17. The apparatus of claim 1, the amplifier comprises a driver amplifier or a low noise amplifier (LNA).

18. The apparatus of claim 1, the first and second matching circuits provide impedance matching for multiple frequency bands.

19. A wireless communication device comprising:

a first matching circuit comprising multiple stages configured for selectively coupling in series and to a first node;

a second matching circuit comprising multiple stages configured for selectively coupling in series and to a second node;

a power amplifier coupled to the first and second matching circuits, the first matching circuit provides input impedance matching for the power amplifier, and the second matching circuit provides output impedance matching for the power amplifier; and

at least one switch coupled between the first and second nodes and to bypass or select the power amplifier.

20. The apparatus of claim 19, the first node has a first impedance and the second node has a second impedance matching the first impedance.

21. The apparatus of claim 19, further comprising:

a second power amplifier coupled in parallel with the power amplifier and further to the first and second matching circuits.

22. The apparatus of claim 21, the second matching circuit comprising

a first input stage coupled to the power amplifier and to provide a first output radio frequency (RF) signal in a first mode,

a second input stage coupled to the second power amplifier and to provide a second output RF signal in a second mode, and

a second stage coupled to the first and second input stages via switches and to provide a third output RF signal in a third mode.

23. A method of performing impedance matching, comprising:

performing input impedance matching for an amplifier with a first matching circuit comprising multiple stages configured for selectively coupling in series;

performing output impedance matching for the amplifier with a second matching circuit comprising multiple stages configured for selectively coupling in series; and

selectively bypassing the amplifier from within the first matching circuit to within the second matching circuit.

24. The method of claim 23, further comprising:

bypassing or selecting the amplifier with at least one switch coupled between first and second nodes having a common impedance, the first node being between two stages in the first matching circuit, and the second node being between two stages in the second matching circuit.

25. The method of claim 23, further comprising:

performing input impedance matching for a second amplifier with the first matching circuit, the second amplifier being coupled in parallel with the amplifier; and

performing output impedance matching for the second amplifier with the second matching circuit.

26. The apparatus of claim 25, further comprising:

providing a first output radio frequency (RF) signal with a first input stage of the second matching circuit coupled to the amplifier in a first mode;

providing a second output RF signal with a second input stage of the second matching circuit coupled to the second amplifier in a second mode; and

providing a third output RF signal with a second stage of the second matching circuit coupled to the first and second input stages in a third mode.

27. An apparatus comprising:

means for performing input impedance matching for an amplifier with a first matching circuit comprising multiple stages configured for selectively coupling in series;

means for performing output impedance matching for the amplifier with a second matching circuit comprising multiple stages configured for selectively coupling in series; and

means for selectively bypassing the amplifier from within the first matching circuit to within the second matching circuit.