Host interface for imaging arrays

• US 8,537,242 B2
• Filed: 10/27/2005
• Issued: 09/17/2013
• Est. Priority Date: 01/21/2000
• Status: Active Grant

• Current Assignee: Cedar Lane Technologies Inc.
• Original Assignee: Harusaki Technologies LLC (Intellectual Ventures LLC)
• Inventors: Suska, Mark
• Primary Examiner(s): DIEP, TRUNG T
• Application Number:
  US11/259,791
• Publication Number:
  US 20060044435A1
• Time in Patent Office: 2,882 Days
• Field of Search: 348/241, 348/294, 348/302, 348/307, 348/308, 348/311, 348/207.1, 348/333.05, 348/222.1, 348/231.3, 348/231.99, 348/312, 348/317, 348/203, 348/246
• US Class Current: 348/231.1
• CPC Class Codes: H04N 23/72 Combination of two or more compensation controls
• CPC Class Codes: H04N 23/74 by influencing the scene brightness using illuminating means
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An interface for receiving data from an image sensor having an imaging array and a clock generator and for transferring the data to a processor system is described. The interface comprises a memory for storing the imaging array data and the clocking signals at a rate determined by the clocking signals. In response to the quantity of data in the memory, a signal generator generates a signal for transmission to the processor system and a circuit controls the transfer of the data from the memory at a rate determined by the processor system. The memory may be a first-in first-out (FIFO) buffer or an addressable memory. The interface is preferably integrated on the same die as the image sensor. The signal generator may generate either an interrupt signal for transmission to the processor system or a bus request signal for transmission to a bus arbitration unit for the processor system.

Claims

1. A method of processing imaging signals, the method comprising:

receiving image data from an imaging array;

storing the image data in a FIFO memory;

updating a FIFO counter to maintain a count of the image data in the FIFO memory in response to memory reads and writes;

comparing the count of the FIFO counter with a FIFO limit;

generating an interrupt signal to request a processor to transfer image data from the FIFO memory in response to an interrupt enable signal being valid and the count of the FIFO counter having a predetermined relationship to the FIFO limit; and

transferring image data from the FIFO memory to the processor in response to the interrupt signal.

2. The method of claim 1, further comprising:

generating a FIFO limit signal, the interrupt enable signal, and an output bus width signal.

3. The method of claim 1, wherein said transferring image data comprises transferring image data from the FIFO memory to the processor in response to receiving a command from the processor.

4. The method of claim 1, further comprising:

storing the image data in the FIFO memory at a first rate based on clocking signals associated with the image array; and

transferring the image data from the FIFO memory at a second rate that is faster than the first rate.

5. The method of claim 1, further comprising:

storing the image data in the FIFO memory at a first rate associated with the image array; and

transferring the image data from the FIFO memory to the processor at a second rate associated with the processor.

6. The method of claim 1, further comprising:

receiving clocking signals associated with the image data;

storing the image data and the clocking signals in the FIFO memory at a first rate based on the clocking signals; and

transferring the image data and the clocking signals from the FIFO memory to the processor at a second rate that is faster than the first rate.

7. The method of claim 6, wherein the clock signals comprise at least one video system clock signal, row clock signal, or frame clock signal.

8. A method of processing imaging signals, the method comprising:

receiving image data from an imaging array;

storing the image data in a FIFO memory;

updating a FIFO counter to maintain a count of the image data in the FIFO memory in response to memory reads and writes;

comparing the count of the FIFO counter with a FIFO limit;

generating, in response to the count of the FIFO counter having a predetermined relationship to the FIFO limit, a bus request signal to request a bus arbitration unit to grant access to an output bus; and

transferring image data from the FIFO memory to the output bus in response to receiving a grant signal from the bus arbitration unit.

9. The method of claim 8, further comprising:

generating a FIFO limit signal and an output bus width signal.

10. The method of claim 8, further comprising:

storing the image data in the FIFO memory at a first rate based on clocking signals associated with the image array; and

transferring the image data from the FIFO memory at a second rate that is faster than the first rate.

11. The method of claim 8, further comprising:

storing the image data in the FIFO memory at a first rate associated with the image array; and

transferring the image data from the FIFO memory to a processing system at a second rate associated with the processing system.

12. The method of claim 8, further comprising:

receiving clocking signals associated with the image data;

storing the image data and the clocking signals in the FIFO memory at a first rate based on the clocking signals; and

transferring the image data and the clocking signals from the FIFO memory to a processing system at a second rate that is faster than the first rate.

13. The method of claim 8, wherein the clock signals comprise at least one video system clock signal, row clock signal, or frame clock signal.

14. A method of processing imaging signals, the method comprising:

receiving, from an imaging array, image data and clocking signals associated with the image data;

storing the image data and the associated clocking signals in a memory at a rate based on the associated clocking signals, wherein the associated clocking signals comprise at least one video system clock signal, row clock signal, or frame clock signal;

generating a request to transfer image data and associated clocking signals from the memory in response to a predetermined amount of data being stored in the memory; and

transferring image data and associated clocking signals from the memory in response to the request.

15. The method of claim 14, wherein said generating a request comprises generating an interrupt signal that requests a processor to download image data and associated clocking signals from the memory.

16. The method of claim 14, wherein the memory is a FIFO memory.

17. The method of claim 16, further comprising:

generating a FIFO limit signal, an interrupt enable signal, and an output bus width signal.

18. The method of claim 16, further comprising:

updating a FIFO counter to maintain a count of data in the FIFO memory in response to FIFO memory reads and writes.

19. The method of claim 18, further comprising:

comparing the count of the FIFO counter with a FIFO limit;

sending an interrupt signal to a processor in response to an interrupt enable signal being valid and the count of the FIFO counter having a predetermined relationship to the FIFO limit; and

transferring image data and associated clocking signals from the memory to the processor in response to receiving a command from the processor.

20. The method of claim 18, further comprising:

comparing the count of the FIFO counter with a FIFO limit;

sending a bus request signal to a bus arbitration unit in response to the count of the FIFO counter having a predetermined relationship to the FIFO limit; and

transferring image data and associated clocking signals from the memory to an output bus in response to receiving a grant signal from the bus arbitration unit.

21. The method of claim 14, further comprising:

transferring the image data and associated clocking signals from the memory at a second rate that is faster than the rate of said storing.

22. The method of claim 14, further comprising:

transferring the image data and associated clocking signals from the memory to a processing system at a second rate associated with the processing system.

23. The method of claim 14, further comprising:

transferring the image data and the associated clocking signals from the memory to a processing system at a second rate that is faster than the rate of said storing.