Low off-state leakage current semiconductor memory device

• US 8,537,600 B2
• Filed: 07/27/2011
• Issued: 09/17/2013
• Est. Priority Date: 08/04/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsubayashi, Daisuke
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): BUDD, PAUL A
• Application Number:
  US13/191,934
• Publication Number:
  US 20120032162A1
• Time in Patent Office: 783 Days
• Field of Search: 257/5, 365/149, 365/186, 365/187
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object is to provide a semiconductor device which can hold stored data even when not powered and which achieves high integration by reduction of the number of wirings. The semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, e.g., an oxide semiconductor material which is a wide bandgap semiconductor. When a semiconductor material which allows a sufficient reduction in the off-state current of a transistor is used, data can be held for a long period. One line serves as the word line for writing and the word line for reading and one line serves as the bit line for writing and the bit line for reading, whereby the number of wirings is reduced. Accordingly, the storage capacity per unit area is increased.

Claims

1. A semiconductor device comprising:

a source line;

n bit lines, n being a natural number;

m memory cells electrically connected in series between the source line and the bit lines, m being a natural number;

m+1 word lines;

a first selection line and a second selection line;

a first selection transistor comprising a gate electrode electrically connected to the first selection line; and

a second selection transistor comprising a gate electrode electrically connected to the second selection line;

wherein the memory cells each comprises;

a first transistor comprising a substrate including a semiconductor material, a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode; and

a capacitor,

wherein the source line is electrically connected to the first source electrode in a m-th memory cell through the second selection transistor,

wherein a first bit line is electrically connected to the first drain electrode of a first memory cell through the first selection transistor and is electrically connected to the second drain electrode of the first memory cell,

wherein a first word line is electrically connected to the second gate electrode of the first memory cell,

wherein a k-th word line is electrically connected to the second gate electrode of a k-th memory cell and is electrically connected to one electrode of the capacitor in a (k−

1)-th memory cell, k being a natural number of greater than or equal to 2 and less than or equal to m,

wherein the first drain electrode of the k-th memory cell is electrically connected to the first source electrode of the (k−

1)-th memory cell, and

wherein the first gate electrode of the m-th memory cell, the second source electrode of the m-th memory cell, and the other electrode of the capacitor of the m-th memory cell are electrically connected to one other.

2. The semiconductor device according to claim 1,

wherein the first transistor comprises:

a channel formation region provided in the substrate including a semiconductor material;

impurity regions between which the channel formation region is provided;

a first gate insulating layer over the channel formation region; and

the first gate electrode provided over the first gate insulating layer so as to overlap with the channel formation region.

3. The semiconductor device according to claim 1,

wherein the second source electrode and the second drain electrode are electrically connected to the oxide semiconductor layer;

wherein the second gate electrode overlaps with the oxide semiconductor layer, and

wherein a second gate insulating layer is formed between the oxide semiconductor layer and the second gate electrode.

4. The semiconductor device according to claim 1, wherein the second transistor has a conductivity type different from a conductivity type of the first transistor.

5. The semiconductor device according to claim 4, wherein the second transistor is a p-channel transistor.

6. The semiconductor device according to claim 1, wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

7. The semiconductor device according to claim 1, wherein the semiconductor material is silicon.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes an oxide semiconductor material including In, Ga and Zn or an oxide semiconductor material including In, Sn and Zn.

9. The semiconductor device according to claim 1, wherein buffer layers having n-type conductivity are formed between the second source electrode and the oxide semiconductor layer and between the second drain electrode and the oxide semiconductor layer.

10. The semiconductor device according to claim 1, wherein the oxide semiconductor includes an oxide including a crystal with c-axis alignment.

11. A semiconductor device comprising:

a source line;

n bit lines, n being a natural number;

m memory cells electrically connected in series between the source line and the bit lines, m being a natural number;

m+1 word lines;

a first selection line and a second selection line;

a first selection transistor comprising a gate electrode electrically connected to the first selection line; and

a second selection transistor comprising a gate electrode electrically connected to the second selection line;

wherein the memory cells each comprises;

a first transistor comprising a substrate including a semiconductor material, a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode; and

a capacitor including the second source electrode, the oxide semiconductor, the second gate insulating layer, an insulating layer over the second gate insulating layer and an electrode over the insulating layer,

wherein the source line is electrically connected to the first source electrode in a m-th memory cell through the second selection transistor,

wherein a first bit line is electrically connected to the first drain electrode of a first memory cell through the first selection transistor and is electrically connected to the second drain electrode of the first memory cell,

wherein a first word line is electrically connected to the second gate electrode of the first memory cell,

wherein a k-th word line is electrically connected to the second gate electrode of a k-th memory cell and is electrically connected to one electrode of the capacitor in a (k−

1)-th memory cell, k being a natural number of greater than or equal to 2 and less than or equal to m,

wherein the first drain electrode of the k-th memory cell is electrically connected to the first source electrode of the (k−

1)-th memory cell, and

wherein the first gate electrode of the m-th memory cell, the second source electrode of the m-th memory cell, and the other electrode of the capacitor of the m-th memory cell are electrically connected to one other.

12. The semiconductor device according to claim 11,

wherein the first transistor comprises:

a channel formation region provided in the substrate including a semiconductor material;

impurity regions between which the channel formation region is provided;

a first gate insulating layer over the channel formation region; and

the first gate electrode provided over the first gate insulating layer so as to overlap with the channel formation region.

13. The semiconductor device according to claim 11,

wherein the second source electrode and the second drain electrode are electrically connected to the oxide semiconductor layer;

wherein the second gate electrode overlaps with the oxide semiconductor layer, and

wherein a second gate insulating layer is formed between the oxide semiconductor layer and the second gate electrode.

14. The semiconductor device according to claim 11, wherein the second transistor has a conductivity type different from a conductivity type of the first transistor.

15. The semiconductor device according to claim 14, wherein the second transistor is a p-channel transistor.

16. The semiconductor device according to claim 11, wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

17. The semiconductor device according to claim 11, wherein the semiconductor material is silicon.

18. The semiconductor device according to claim 11, wherein the oxide semiconductor layer includes an oxide semiconductor material including In, Ga and Zn or an oxide semiconductor material including In, Sn and Zn.

19. The semiconductor device according to claim 11, wherein buffer layers having n-type conductivity are formed between the second source electrode and the oxide semiconductor layer and between the second drain electrode and the oxide semiconductor layer.

20. The semiconductor device according to claim 11, wherein the oxide semiconductor includes an oxide including a crystal with c-axis alignment.