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Low off-state leakage current semiconductor memory device

  • US 8,537,600 B2
  • Filed: 07/27/2011
  • Issued: 09/17/2013
  • Est. Priority Date: 08/04/2010
  • Status: Expired due to Fees
First Claim
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1. A semiconductor device comprising:

  • a source line;

    n bit lines, n being a natural number;

    m memory cells electrically connected in series between the source line and the bit lines, m being a natural number;

    m+1 word lines;

    a first selection line and a second selection line;

    a first selection transistor comprising a gate electrode electrically connected to the first selection line; and

    a second selection transistor comprising a gate electrode electrically connected to the second selection line;

    wherein the memory cells each comprises;

    a first transistor comprising a substrate including a semiconductor material, a first gate electrode, a first source electrode, and a first drain electrode;

    a second transistor comprising an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode; and

    a capacitor,wherein the source line is electrically connected to the first source electrode in a m-th memory cell through the second selection transistor,wherein a first bit line is electrically connected to the first drain electrode of a first memory cell through the first selection transistor and is electrically connected to the second drain electrode of the first memory cell,wherein a first word line is electrically connected to the second gate electrode of the first memory cell,wherein a k-th word line is electrically connected to the second gate electrode of a k-th memory cell and is electrically connected to one electrode of the capacitor in a (k−

    1)-th memory cell, k being a natural number of greater than or equal to 2 and less than or equal to m,wherein the first drain electrode of the k-th memory cell is electrically connected to the first source electrode of the (k−

    1)-th memory cell, andwherein the first gate electrode of the m-th memory cell, the second source electrode of the m-th memory cell, and the other electrode of the capacitor of the m-th memory cell are electrically connected to one other.

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