Memory controller with selective data transmission delay

• US 8,537,601 B2
• Filed: 07/06/2012
• Issued: 09/17/2013
• Est. Priority Date: 04/24/2001
• Status: Expired due to Fees

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/543,779
• Publication Number:
  US 20120287725A1
• Time in Patent Office: 438 Days
• Field of Search: 365/149, 365/150, 365/191, 365/194, 365/189.02, 365/230.02
• US Class Current: 365/149
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A DRAM controller component generates a timing signal and transmits, to a DRAM, write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, a clock signal that requires a second time interval to propagate from the DRAM controller component to the DRAM, and a write command, associated with the write data, to be sampled by the DRAM on one or more edges of the clock signal. The DRAM controller component includes series-coupled delay elements to generate respective incrementally delayed signals, and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.

Claims

1. A memory controller component that generates a timing signal, the memory controller component to control a dynamic random access memory component (DRAM), the memory controller component comprising:

transmit circuitry to transmit, to the DRAM;

write data to be sampled by the DRAM on one or more edges of the timing signal, the write data requiring a first time interval to propagate from the memory controller component to the DRAM;

a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and

a write command to be sampled by the DRAM on one or more edges of the first clock signal, the write command associated with the write data;

a plurality of delay elements coupled in series to respectively generate a plurality of incrementally delayed signals; and

a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.

2. The memory controller component of claim 1, wherein the delay of each delay element is identical.

3. The memory controller component of claim 1, wherein the plurality of delay elements is part of a delay locked loop.

4. The memory controller component of claim 3, wherein the delay locked loop adjusts respective delays of the delay elements to control a total delay of the delay locked loop.

5. The memory controller component of claim 1, further comprising a shift register to store the write data and coupled to the multiplexer to receive the one of the delayed signals therefrom.

6. The memory controller component of claim 5, wherein the transmit circuitry comprises a buffer to transmit the write data, the buffer coupled to an output of the shift register to receive the write data therefrom.

7. The memory controller component of claim 1, wherein the timing signal is a strobe signal.

8. The memory controller component of claim 1, wherein the timing signal is a second clock signal.

9. A method of operation within a memory controller component that outputs a timing signal to a dynamic random access memory component (DRAM), the method comprising:

transmitting, to the DRAM;

write data to be sampled by the DRAM on one or more edges of the timing signal, the write data requiring a first time interval to propagate from the memory controller component to the DRAM;

a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and

a write command to be sampled by the DRAM on one or more edges of the first clock signal, the write command associated with the write data;

generating a plurality of incrementally delayed signals; and

selecting one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.

10. The method of claim 9, wherein generating a plurality of incrementally delayed signals comprises generating the plurality of incrementally delayed signals in a plurality of delay elements coupled in series, each of the delay elements generating a respective one of the delayed signals.

11. The method of claim 10, wherein the delay of each delay element is identical.

12. The method of claim 9, wherein the plurality of delay elements is part of a delay locked loop.

13. The method of claim 12, wherein the delay locked loop adjusts respective delays of the delay elements to control a total delay of the delay locked loop.

14. The method of claim 9, further comprising storing the write data in a shift register and shifting the write data out of the shift register in response to transitions of the one of the delayed signals.

15. The method of claim 14, wherein transmitting the write data comprises generating an output signal to be conveyed to the DRAM according to each bit of the write data shifted out of the shift register.

16. The method of claim 9, wherein the timing signal is a strobe signal.

17. The method of claim 9, wherein the timing signal is a second clock signal.

18. A memory controller component that generates a timing signal, the memory controller component to control a dynamic random access memory component (DRAM), the memory controller component comprising:

means for transmitting, to the DRAM;

write data to be sampled by the DRAM on one or more edges of the timing signal, the write data requiring a first time interval to propagate from the memory controller component to the DRAM;

a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and

a write command to be sampled by the DRAM on one or more edges of the first clock signal, the write command associated with the write data;

means for generating a plurality of incrementally delayed signals; and

means for selecting one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.