Data cells with drivers and methods of making and operating the same

• US 8,537,608 B2
• Filed: 09/12/2012
• Issued: 09/17/2013
• Est. Priority Date: 04/03/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US13/612,361
• Publication Number:
  US 20130005102A1
• Time in Patent Office: 370 Days
• Field of Search: 365/149, 365/189.011, 438/585, 257/E21.158
• US Class Current: 365/174
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate.

Claims

1. A method, comprising:

forming a plurality of trenches into semiconductive material of a substrate, and forming dielectric material in the trenches;

after forming the dielectric material in the trenches, etching into the semiconductive material to form a plurality of trench segments in the semiconductive material between the trenches; and

forming a plurality of fins, wherein the trench segments extend between pairs of adjacent fins but not between more than four fins.

2. The method of claim 1, wherein the trench segments do not extend between more than two adjacent fins.

5. The method of claim 1, comprising forming gates adjacent sides of the plurality of fins.

7. The method of claim 1 comprising forming the plurality of trench segments and the plurality of trenches to be longitudinally elongated parallel one another.

11. The method of claim 1 wherein the etching is conducted using multiple etching steps.

12. The method of claim 1 wherein the trench segments are longitudinally elongated and the dielectric material projects outwardly of the trenches, the forming of the trench segments comprising self-aligning the trench segments laterally using spacers that are laterally against the dielectric material that projects outward of the trenches.

13. The method of claim 1 comprising conducting a threshold voltage implant into a bottom of at least one sidewall of the trench segments.

14. The method of claim 13 wherein the implant is conducted before forming the plurality of fins.

15. The method of claim 1 comprising conducting a threshold voltage implant into a bottom of opposing sidewalls of the trench segments.

16. The method of claim 15 wherein the implant is conducted before forming the plurality of fins.

18. The method of claim 11 wherein the etching comprises use of TMAH.

3. A method, comprising:

forming a plurality of isolation trenches in a substrate;

forming a plurality of trench segments between the isolation trenches;

forming a plurality of fins, wherein the trench segments extend between pairs of adjacent fins but not between more than four fins; and

forming column gates in the trench segments before forming the plurality of fins.

4. The method of claim 3, comprising forming a notch between the isolation trenches.

8. The method of claim 3 comprising forming gate dielectric in the trench segments before forming the plurality of fins.

10. The method of claim 4 wherein the trenches are longitudinally elongated parallel one another, the notch being longitudinally elongated perpendicular the trenches.

6. A method, comprising:

forming a plurality of trenches into semiconductive material of a substrate, and forming dielectric material in the trenches;

after forming the dielectric material in the trenches, forming a plurality of trench segments into the semiconductive material between the trenches;

forming a plurality of fins, wherein the trench segments extend between pairs of adjacent fins but not between more than four fins; and

forming gates adjacent sides of the plurality of fins, wherein forming the gates comprises depositing conductive material over horizontal surfaces and adjacent sides of the plurality of fins, followed by anisotropically etching the conductive material to remove the conductive material from horizontal surfaces and leave the conductive material adjacent sides of the plurality of fins.

9. A method, comprising:

forming a plurality of trenches into semiconductive material of a substrate, and forming dielectric material in the trenches;

after forming the dielectric material in the trenches, forming a plurality of trench segments into the semiconductive material between the trenches; and

forming a plurality of fins, wherein the trench segments extend between pairs of adjacent fins but not between more than four fins, the trench segments individually having a bottom comprising semiconductive material, and comprising angle ion implanting into semiconductive material at the bottoms of the plurality of trench segments to suppress formation of parasitic devices.

17. A method, comprising:

forming a plurality of longitudinally elongated and parallel isolation trenches into semiconductive material of a substrate, and forming dielectric material in the trenches;

after forming the dielectric material in the trenches, etching into the semiconductive material to form a plurality of longitudinally elongated and spaced trench segments in the semiconductive material between the trenches, the trench segments extending longitudinally parallel the isolation trenches; and

forming a plurality of fins, wherein the trench segments extend between pairs of adjacent fins but not between more than four fins.