Nonvolatile semiconductor memory device

• US 8,537,615 B2
• Filed: 05/31/2011
• Issued: 09/17/2013
• Est. Priority Date: 11/29/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Maeda, Takashi
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US13/149,139
• Publication Number:
  US 20120134210A1
• Time in Patent Office: 840 Days
• Field of Search: 365/185.11, 365/185.17, 365/185.05, 365/218
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a memory cell array including a plurality of memory blocks;

a plurality of memory strings disposed in a matrix in each of the plurality of memory blocks, each memory string including a plurality of electrically rewritable memory transistors connected in series;

a drain side select transistor having one end thereof connected to a first end of the memory string;

a source side select transistor having one end thereof connected to a second end of the memory string;

a plurality of word lines disposed so as to be commonly connected to the plurality of memory strings disposed in one of the plurality of memory blocks;

a plurality of bit lines each extending in a first direction and each connected to the other end of the drain side select transistor in the plurality of memory blocks;

a source line connected to the other end of the source side select transistor;

a drain side select gate line disposed along a second direction as a longer direction thereof and so as to commonly connect a gate of the drain side select transistor aligned in the second direction, the second direction being orthogonal to the first direction;

a source side select gate line disposed along the second direction as a longer direction thereof and so as to commonly connect a gate of the source side select transistor aligned in the second direction; and

a control circuit configured to control a voltage applied to the plurality of memory blocks,

each of the plurality of memory strings comprising;

a columnar semiconductor layer including a columnar portion extending in a perpendicular direction with respect to a substrate, the columnar semiconductor layer being configured to function as a body of the memory transistors;

a charge storage layer formed so as to surround a side surface of the columnar portion and configured to allow storage of a charge; and

a word line conductive layer formed so as to surround the side surface of the columnar portion with the charge storage layer interposed therebetween, the word line conductive layer being configured to function as a gate of the memory transistors and as the word lines,

wherein a plurality of the memory strings that are connected to a plurality of the drain side select transistors and a plurality of the source side select transistors which are commonly connected to one of the drain side select gate lines and one of the source side select gate lines, respectively, configure one sub-block, and

wherein, for execution of an erase operation of selectively erasing at least one of the sub-blocks in the memory blocks, the control circuit is configured to;

apply, in a first sub-block as a selected sub-block, a first voltage to the bit line and the source line, a second voltage smaller than the first voltage to the word lines, and a third voltage lower than the first voltage by a certain value to the drain side select gate line and the source side select gate line, thereby performing the erase operation in the first sub-block; and

apply, in a second sub-block as an unselected sub-block, the second sub-block existing in an identical memory block to that of the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

2. The nonvolatile semiconductor memory device according to claim 1,

wherein the third voltage is set so as to cause a GIDL (Gate Induced Drain Leakage) current to be generated due to a potential difference between the first voltage and the third voltage, and

wherein the fourth voltage is set such that generation of a GIDL current due to a potential difference between the first voltage and the fourth voltage is prevented.

3. The nonvolatile semiconductor memory device according to claim 1,

wherein the drain side select transistor includes a first drain side select transistor and a second drain side select transistor, the second drain side select transistor being connected in series to the first drain side select transistor and having one end thereof connected to the bit lines,

wherein the source side select transistor includes a first source side select transistor and a second source side select transistor, the second source side select transistor being connected in series to the first source side select transistor and having one end thereof connected to the source line, and

wherein, for execution of an erase operation of selectively erasing at least one of the sub-blocks in the memory blocks, the control circuit is configured to:

apply, in the first sub-block, the third voltage to a second drain side select gate line and a second source side select gate line, the second drain side select gate line being connected to a gate of the second drain side select transistor, the second source side select gate line being connected to agate of the second source side select transistor, while applying, in the first sub-block, a fifth voltage substantially intermediate between the fourth voltage and the second voltage to a first drain side select gate line and a first source select gate line, the first drain side select gate line being connected to a gate of the first drain side select transistor, the first source side select gate line being connected to a gate of the first source side select transistor;

apply, in the second sub-block, the fourth voltage to the second drain side select gate line and the second source side select gate line, while applying, in the second sub-block, the fifth voltage to the first drain side select gate line and the first source side select gate line.

4. The nonvolatile semiconductor memory device according to claim 3,

wherein the third voltage is set so as to cause a GIDL (Gate Induced Drain Leakage) current to be generated due to a potential difference between the first voltage and the third voltage, and

wherein the fourth voltage is set such that generation of a GIDL current due to a potential difference between the first voltage and the fourth voltage is prevented.

5. The nonvolatile semiconductor memory device according to claim 3,

wherein the first drain side select gate line and the first source side select gate line of each of a plurality of the sub-blocks are commonly connected to the first drain side select gate line and the first source side select gate line in other sub-blocks.

6. The nonvolatile semiconductor memory device according to claim 5,

wherein a plurality of the first drain side select transistors are connected in series to one second drain side select transistor, and a plurality of the first source side select transistors are connected in series to one second source side select transistor, and

wherein, for execution of an erase operation of selectively erasing at least one of the sub-blocks in the memory blocks, the control circuit is configured to:

set a value of a voltage applied to the gate of each of the first drain side select transistors such that a first drain side select transistor closer to a bit line side is applied with a larger voltage to its gate as compared to a gate of a first drain side select transistor formed on the farther side from the bit line; and

set a value of a voltage applied to the gate of each of the first source side select transistors such that a first source side select transistor closer to a source line side is applied with a larger voltage to its gate as compared to a gate of the first source side select transistor formed on the farther side from the source line.

7. The nonvolatile semiconductor memory device according to claim 1,

wherein the drain side select transistor includes a first drain side select transistor and a second drain side select transistor, the first drain side select transistor being connected to a first end of the memory string, and the second drain side select transistor being connected in series to the first drain side select transistor,

wherein the source side select transistor includes a first source side select transistor and a second source side select transistor, the first source side select transistor being connected to a second end of the memory string, and the second source side select transistor being connected in series to the first source side select transistor, and

wherein, for execution of an erase operation of selectively erasing at least one of the sub-blocks in the memory blocks, the control circuit is configured to:

apply, in the first sub-block, the third voltage to a first drain side select gate line, a second drain side select gate line, a first source side select gate line, and a second source side select gate line, the first drain side select gate line being connected to a gate of the first drain side select transistor, the second drain side select gate line being connected a gate of the second drain side select transistor, the first source side select gate line being connected to a gate of the first source side select transistor, and the second source side select gate line being connected to a gate of the second source side select transistor, and

apply, in the second sub-block, the fourth voltage to the second drain side select gate line and the second source side select gate line, while applying the fifth voltage to the first drain side select gate line and the first source side select gate line.

8. The nonvolatile semiconductor memory device according to claim 7,

wherein the third voltage is set so as to cause a GIDL (Gate Induced Drain Leakage) current to be generated due to a potential difference between the first voltage and the third voltage, and

wherein the fourth voltage is set such that generation of a GIDL current due to a potential difference between the first voltage and the fourth voltage is prevented.

9. The nonvolatile semiconductor memory device according to claim 7,

wherein a plurality of the first drain side select transistors are connected in series to one second drain side select transistor, and a plurality of the first source side select transistors are connected in series to one second source side select transistor, and

wherein, for execution of an erase operation of selectively erasing at least one of the sub-blocks in the memory blocks, the control circuit is configured to:

set a value of the fifth voltage applied to the gate of each of the first drain side select transistors such that a first drain side select transistor closer to a bit line side is applied with a larger voltage as the fifth voltage to its gate as compared to a gate of a first drain side select transistor formed on the farther side from the bit line; and

set a value of the fifth voltage applied to the gate of each of the first source side select transistors such that a first source side select transistor closer to a source line side is applied with a larger voltage as the fifth voltage to its gate as compared to a gate of the first source side select transistor formed on the farther side from the source line.

10. The nonvolatile semiconductor memory device according to claim 1,

wherein each of the plurality of memory strings further comprises:

a first dummy transistor connected to the drain side select transistor and not used for data storage; and

a second dummy transistor connected to the source side select transistor and not used for data storage, and

wherein, for execution of an erase operation of selectively erasing at least one of the sub-blocks in the memory blocks, the control circuit is configured to;

apply, in the first sub-block, the third voltage to the drain side select gate line and the source side select gate line;

apply, in the first-sub-block, a fifth voltage substantially intermediate between the fourth voltage and the second voltage to a first dummy word line and a second dummy line, the first dummy line being connected to a gate of the first dummy transistor, the second dummy line being connected to a gate of the second dummy transistor; and

apply, in the second sub-block, the fourth voltage to the drain side select gate line and the source side select gate line, while applying the fifth voltage to the first dummy word line and the second dummy word line.

11. The nonvolatile semiconductor memory device according to claim 10,

wherein the third voltage is set so as to cause a GIDL (Gate Induced Drain Leakage) current to be generated due to a potential difference between the first voltage and the third voltage, and

wherein the fourth voltage is set such that generation of a GIDL current due to a potential difference between the first voltage and the fourth voltage is prevented.

12. The nonvolatile semiconductor memory device according to claim 10,

wherein the first dummy transistor and the second dummy transistor each comprises:

the columnar semiconductor layer;

the charge storage layer; and

a dummy word line conductive layer configured to function as the first dummy word line or the second dummy word line.

13. The nonvolatile semiconductor memory device according to claim 1,

wherein each of the plurality of memory strings further comprises:

a third dummy transistor connected in series to the memory transistors and not used for data storage;

a fourth dummy transistor connected in series to the third dummy transistor, the fourth dummy transistor having one end thereof connected to the drain side select transistor and not being used for data storage;

a fifth dummy transistor connected in series to the memory transistors and not used for data storage; and

a sixth dummy transistor connected in series to the fifth dummy transistor, the sixth dummy transistor having one end thereof connected to the source side select transistor and not being used for data storage,

wherein, for execution of an erase operation of selectively erasing at least one of the sub-blocks in the memory blocks, the control circuit is configured to;

apply, in the first sub-block, the third voltage to a fourth dummy word line and a sixth dummy word line, the fourth dummy word line being connected to a gate of the fourth dummy transistor, and the sixth dummy word line being connected to a gate of the sixth dummy transistor, while applying a fifth voltage substantially intermediate between the fourth voltage and the second voltage to a third dummy word line and a fifth dummy word line, the third dummy word line being connected to a gate of the third dummy transistor, the fifth dummy word line being connected to a gate of the fifth dummy transistor;

and apply, in the second sub-block, the fourth voltage to the fourth dummy word line and the sixth dummy word line, while applying the fifth voltage to the third dummy word line and the fifth dummy word line.

14. The nonvolatile semiconductor memory device according to claim 13,

wherein the third voltage is set so as to cause a GIDL (Gate Induced Drain Leakage) current to be generated due to a potential difference between the first voltage and the third voltage, and

wherein the fourth voltage is set such that generation of a GIDL current due to a potential difference between the first voltage and the fourth voltage is prevented.

15. The nonvolatile semiconductor memory device according to claim 13,

wherein a plurality of the third dummy transistors are connected in series to one fourth dummy transistor, and a plurality of the fifth dummy transistors are connected in series to one sixth dummy transistor, and

wherein, for execution of an erase operation of selectively erasing at least one of the sub-blocks in the memory blocks, the control circuit is configured to:

set a value of a voltage applied to the gate of each of the third dummy transistors such that a third dummy transistor closer to a bit line side is applied with a larger voltage to its gate as compared to a gate of a third dummy transistor formed on the farther side from the bit line; and

set a value of a voltage applied to the gate of each of the fifth dummy transistors such that a fifth dummy transistor closer to a source line side is applied with a larger voltage to its gate as compared to a gate of the fifth dummy transistor formed on the farther side of the source line.

16. The nonvolatile semiconductor memory device according to claim 10,

wherein the first dummy word line and the second dummy word line of each of a plurality of the sub-blocks are commonly connected to the first dummy word line and the second dummy word line in other sub-blocks.

17. The nonvolatile semiconductor memory device according to claim 1,

wherein a distance between the drain side select gate line or the source side select gate line and the word lines is set larger than a distance between the word lines.

18. The nonvolatile semiconductor memory device according to claim 1,

wherein the control circuit is configured to supply a fifth voltage substantially intermediate between the fourth voltage and the second voltage to the bit lines, source line, drain side select gate line, or source side select gate line, prior to supplying a target voltage to the bit lines, source line, drain side select gate line, or source side select gate line.

19. A method for controlling a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device comprising:

a memory cell array including a plurality of memory blocks;

a plurality of memory strings disposed in a matrix in each of the plurality of memory blocks, each memory string including a plurality of electrically rewritable memory transistors connected in series;

a drain side select transistor having one end thereof connected to a first end of the memory string;

a source side select transistor having one end thereof connected to a second end of the memory string;

a plurality of word lines disposed so as to be commonly connected to the plurality of memory strings disposed in one of the plurality of memory blocks;

a plurality of bit lines each extending in a first direction and each connected to the other end of the drain side select transistor in the plurality of memory blocks;

a source line connected to the other end of the source side select transistor;

a drain side select gate line disposed along a second direction as a longer direction thereof and so as to commonly connect a gate of the drain side select transistor aligned in the second direction, the second direction being orthogonal to the first direction;

a source side select gate line disposed along the second direction as a longer direction thereof and so as to commonly connect a gate of the source side select transistor aligned in the second direction; and

a control circuit configured to control a voltage applied to the plurality of memory blocks,

each of the plurality of memory strings comprising;

a columnar semiconductor layer including a columnar portion extending in a perpendicular direction with respect to a substrate, the columnar semiconductor layer being configured to function as a body of the memory transistors;

a charge storage layer formed so as to surround a side surface of the columnar portion and configured to allow storage of a charge; and

a word line conductive layer formed so as to surround the side surface of the columnar portion with the charge storage layer interposed therebetween, the word line conductive layer being configured to function as a gate of the memory transistors and as the word lines, and

a plurality of the memory strings that are connected to a plurality of the drain side select transistors and a plurality of the source side select transistors which are commonly connected to one of the drain side select gate lines and one of the source side select gate lines, respectively, configuring one sub-block,

the method comprising;

when an erase operation of selectively erasing at least one of the sub-blocks in the memory blocks is executed,

applying, in a first sub-block as a selected sub-block, a first voltage to the bit lines and the source line, and applying a second voltage smaller than the first voltage to the word lines, and applying a third voltage lower than the first voltage by a certain value to the drain side select gate line and the source side select gate line, thereby performing the erase operation in the first sub-block,

and applying, in a second sub-block as an unselected sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

20. The method for controlling a nonvolatile semiconductor memory device according to claim 19,

wherein the third voltage is set so as to cause a GIDL (Gate Induced Drain Leakage) current to be generated due to a potential difference between the first voltage and the third voltage, and

wherein the fourth voltage is set such that generation of a GIDL current due to a potential difference between the first voltage and the fourth voltage is prevented.