Memory voltage regulator with leakage current voltage control
First Claim
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1. A circuit comprising:
- a first plurality of memory cells, each memory cell of the first plurality of memory cells including a voltage supply terminal coupled to a regulated node;
a second plurality of memory cells;
a voltage regulator coupled to the regulated node to control a voltage of the regulated node, the voltage regulator comprising;
a leakage current measuring circuit, the leakage current measuring circuit including a reference node for providing a measuring voltage that is dependent upon a measured leakage current of the second plurality of memory cells, wherein the voltage regulator uses the measuring voltage in controlling the voltage of the regulated node;
a regulating transistor having a first current terminal coupled to the regulated node and a second current terminal coupled to a power supply node;
an operational amplifier circuit including an inverting input coupled to the reference node, a non-inverting input coupled to the regulated node, and an output coupled to a control terminal of the regulating transistor.
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Abstract
A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.
70 Citations
21 Claims
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1. A circuit comprising:
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a first plurality of memory cells, each memory cell of the first plurality of memory cells including a voltage supply terminal coupled to a regulated node; a second plurality of memory cells; a voltage regulator coupled to the regulated node to control a voltage of the regulated node, the voltage regulator comprising; a leakage current measuring circuit, the leakage current measuring circuit including a reference node for providing a measuring voltage that is dependent upon a measured leakage current of the second plurality of memory cells, wherein the voltage regulator uses the measuring voltage in controlling the voltage of the regulated node; a regulating transistor having a first current terminal coupled to the regulated node and a second current terminal coupled to a power supply node; an operational amplifier circuit including an inverting input coupled to the reference node, a non-inverting input coupled to the regulated node, and an output coupled to a control terminal of the regulating transistor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A circuit comprising:
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a first plurality of memory cells, each memory cell of the first plurality of memory cells including a voltage supply terminal coupled to a regulated node; a second plurality of memory cells; a voltage regulator coupled to the regulated node to control a voltage of the regulated node, the voltage regulator comprising; a leakage current measuring circuit, the leakage current measuring circuit including a reference node for providing a measuring voltage that is dependent upon a measured leakage current of the second plurality of memory cells, wherein the voltage regulator uses the measuring voltage in controlling the voltage of the regulated node; wherein the second plurality of memory cells are usable to store retrievable data.
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8. A circuit comprising:
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a first plurality of memory cells, each memory cell of the first plurality of memory cells including a voltage supply terminal coupled to a regulated node; a second plurality of memory cells; a voltage regulator coupled to the regulated node to control a voltage of the regulated node, the voltage regulator comprising; a leakage current measuring circuit, the leakage current measuring circuit including a reference node for providing a measuring voltage that is dependent upon a measured leakage current of the second plurality of memory cells, wherein the voltage regulator uses the measuring voltage in controlling the voltage of the regulated node; a voltage clamp coupled to the reference node for preventing the measuring voltage of the reference node form rising above a particular value. - View Dependent Claims (9)
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10. A circuit comprising:
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a first plurality of memory cells, each memory cell of the first plurality of memory cells including a voltage supply terminal coupled to a regulated node; a second plurality of memory cells; a voltage regulator coupled to the regulated node to control a voltage of the regulated node, the voltage regulator comprising; a leakage current measuring circuit, the leakage current measuring circuit including a reference node for providing a measuring voltage that is dependent upon a measured leakage current of the second plurality of memory cells, wherein the voltage regulator uses the measuring voltage in controlling the voltage of the regulated node; at least one switch for selectively coupling at least some of the second plurality of memory cells to the reference node in a first switch position and for coupling the at least some of the second plurality of memory cells to the regulated node in a second switch position.
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11. A circuit comprising:
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a first plurality of memory cells, each memory cell of the first plurality of memory cells including a voltage supply terminal coupled to a regulated node; a second plurality of memory cells; a voltage regulator coupled to the regulated node to control a voltage of the regulated node, the voltage regulator comprising; a leakage current measuring circuit, the leakage current measuring circuit including a reference node for providing a measuring voltage that is dependent upon a measured leakage current of the second plurality of memory cells, wherein the voltage regulator uses the measuring voltage in controlling the voltage of the regulated node; an enablement transistor having a first current terminal coupled to the regulated node, a second current electrode coupled to a power supply terminal, and a control terminal for receiving an enablement signal that when in a first state, makes the enablement transistor conductive to pull a voltage of the regulated node to a voltage of the power supply node regardless of the measuring voltage. - View Dependent Claims (12)
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13. A circuit comprising:
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a first plurality of memory cells, each memory cell of the first plurality of memory cells including a voltage supply terminal coupled to a regulated node; a second plurality of memory cells; a voltage regulator coupled to the regulated node to control a voltage of the regulated node, the voltage regulator comprising; a leakage current measuring circuit, the leakage current measuring circuit including a reference node for providing a measuring voltage that is dependent upon a measured leakage current of the second plurality of memory cells, wherein the voltage regulator uses the measuring voltage in controlling the voltage of the regulated node; a resistive circuit having one terminal connected to the reference node and a second terminal connected to a power supply terminal, wherein the measuring voltage is determined by the measured leakage current from the second plurality of memory cells flowing though the resistive circuit. - View Dependent Claims (14, 15)
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16. A circuit comprising:
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a first plurality of memory cells, each memory cell of the first plurality of memory cells including a voltage supply terminal coupled to a regulated node; a second plurality of memory cells; a voltage regulator coupled to the regulated node to control the voltage of the regulated node to control the voltages across the cells of the first plurality of memory cells, the voltage regulator comprising; a leakage current measuring circuit, the leakage current measuring circuit including a reference node for providing a measuring voltage that is dependent upon a measured leakage current of the second plurality of memory cells, wherein the voltage regulator uses the measuring voltage in controlling the voltages across the cells of the first plurality of memory cells to control the leakage current of the first plurality of memory cells; a regulating transistor having a first current terminal coupled to the regulated node and a second current terminal coupled to a power supply node; an operational amplifier circuit including an inverting input coupled to the reference node, a non-inverting input coupled to the regulated node, and an output coupled to a control terminal of the regulating transistor. - View Dependent Claims (17, 18, 19)
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20. A circuit comprising:
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a first plurality of memory cells, each memory cell of the first plurality of memory cells including a voltage supply terminal coupled to a regulated node; a second plurality of memory cells; a voltage regulator coupled to the regulated node to control the voltage of the regulated node to control the voltages across the cells of the first plurality of memory cells, the voltage regulator comprising; a leakage current measuring circuit, the leakage current measuring circuit including a reference node for providing a measuring voltage that is dependent upon a measured leakage current of the second plurality of memory cells, wherein the voltage regulator uses the measuring voltage in controlling the voltages across the cells of the first plurality of memory cells to control the leakage current of the first plurality of memory cells; wherein the second plurality of memory cells are usable to store retrievable data. - View Dependent Claims (21)
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Specification