Reconfigurable equalization architecture for high-speed receivers

• US 8,537,886 B1
• Filed: 07/05/2012
• Issued: 09/17/2013
• Est. Priority Date: 07/05/2012
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Su, Xiaoyan, Narayan, Sriram, Shumarayev, Sergey
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US13/541,917
• Time in Patent Office: 439 Days
• Field of Search: None
• US Class Current: 375/233
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

Systems and methods are disclosed for employing an equalization technique that improves equalizer input sensitivity and which reduces power consumption. In particular, an equalization architecture is described that includes a continuous-time linear equalizer and a decision feedback equalizer, each with offset cancellation that enables the equalizer to be used at high data rates. In addition, the equalization structure has a power-saving mode for bypassing the decision feedback equalizer. These offset cancellation and power-saving features are enabled and controlled using programmable logic on a programmable device.

Claims

1. A programmable integrated circuit device comprising:

a decision feedback equalizer configured to equalize an input signal, wherein the decision feedback equalizer comprises;

a summer circuit configured to sum the input signal with a plurality of signals, wherein the summer circuit includes a first transistor and second transistor arranged as a differential pair;

the first transistor configured to receive the input signal and the second transistor configured to receive a complement of the input signal;

a resistor disposed between the first transistor and the second transistor configured to provide resistor degeneration;

a first current source disposed at a first node connecting the first transistor and the resistor, the first current source configured to provide offset cancellation; and

a second current source disposed at a second node connecting the second transistor and the resistor, the second current source configured to provide offset cancellation; and

logic circuitry configured to control the first current source and the second current source based on stored calibration data.

2. The programmable integrated circuit device of claim 1, wherein the logic circuitry is further configured to:

monitor an output of the summer circuit while varying a first control signal that controls the first current source and the second current source;

detect a minimal level of offset in the output based on the monitoring; and

store an indication of the first control signal as part of the calibration data when the minimal level of offset is detected.

3. The programmable integrated circuit device of claim 1, wherein the summer circuit further comprises:

a third transistor and a fourth transistor arranged as a differential pair, wherein the third transistor is configured to receive a feedback signal and the fourth transistor is configured to receive a complement of the feedback signal;

a third current source disposed at a third node connecting the third transistor and the fourth transistor, the third current source configured to receive a second control signal that controls the third current source; and

a first switch disposed between the third current source and the logic circuitry and a second switch disposed between the third current source and a low voltage;

wherein the logic circuitry is further configured to generate the second control signal and to control the first switch and second switch.

4. The programmable integrated circuit device of claim 3, wherein the logic circuitry is further configured to close the first switch and open the second switch when in a first mode, and to open the first switch and close the second switch when in a second mode.

5. The programmable integrated circuit device of claim 1, wherein the decision feedback equalizer further comprises a switch disposed between the summer circuit and a voltage source, wherein the logic circuitry is further configured to control the switch.

6. The programmable integrated circuit device of claim 1, wherein the summer circuit is a first summer circuit and the plurality of signals is a first plurality of signals, the decision feedback equalizer further comprising:

a second summer circuit configured to sum the input signal with a second plurality of signals;

a stacked multiplexer configured to receive a first internal signal from the first summer circuit, a second internal signal from the second summer circuit, a first delayed output signal, a second delayed output signal, and a clock signal, and to select one of the first internal signal and the second internal signal for output; and

first delay circuitry configured to receive the output of the stacked multiplexer and to output the first delayed output signal; and

second delay circuitry configured to receive the output of the stacked multiplexer and to output the second delayed output signal.

7. The programmable integrated circuit device of claim 6 further comprising:

third delay circuitry configured to receive the output of the stacked multiplexer and to output a third delayed output signal;

fourth delay circuitry configured to receive the output of the stacked multiplexer and to output a fourth delayed output signal; and

a multiplexer configured to receive the third delayed output signal from the third delay circuitry and the fourth delayed output signal from the fourth delay circuitry and to provide one of the third delayed output signal and fourth delayed output signal to the first summer circuit and the second summer circuit.

8. The programmable integrated circuit device of claim 7, wherein the logic circuitry is further configured to control a plurality of switches disposed within the first summer circuit, second summer circuit, the stacked multiplexer, the first delay circuitry, the second delay circuitry, the third delay circuitry, and the fourth delay circuitry.

9. The programmable integrated circuit device of claim 8, wherein the logic circuitry is further configured to:

determine whether the decision feedback equalizer is in a first mode or a second mode;

disable, using the plurality of switches, the second summer circuit, the first delay circuitry, the second delay circuitry, the third delay circuitry, and the fourth delay circuitry when the decision feedback equalizer is in the first mode;

configure, using the plurality of switches, the stacked multiplexer to select the first internal signal for output when the decision feedback equalizer is in the first mode;

enable, using the plurality of switches,

the second summer circuit, the first delay circuitry, the second delay circuitry, the third delay circuitry, and the fourth delay circuitry when the decision feedback equalizer is in the second mode; and

configure, using the plurality of switches, the stacked multiplexer to select one of the first internal signal and the second internal signal for output depending on the first delayed output signal and the second delayed output signal when the decision feedback equalizer is in the second mode.

10. The programmable integrated circuit device of claim 9, wherein the logic circuitry is further configured to:

determine whether the decision feedback equalizer is in a third mode;

disable, using the plurality of switches, the first summer circuit, the first delay circuitry, the second delay circuitry, the third delay circuitry, and the fourth delay circuitry when the decision feedback equalizer is in the third mode; and

configure, using the plurality of switches, the stacked multiplexer to select the second internal signal for output when the decision feedback equalizer is in the third mode.

11. A programmable integrated circuit device comprising:

a continuous time linear equalizer configured to equalize an input signal;

a decision feedback equalizer configured

to receive the equalized input signal and to provide an output signal, wherein the decision feedback equalizer comprises a high path and a low path; and

logic circuitry configured to;

determine whether the decision feedback equalizer is in a bypass mode; and

in response to determining that the decision feedback equalizer is in the bypass mode, (a) disable the low path and (b) provide, using the high path, the equalized input signal as the output signal.

12. The programmable integrated circuit device of claim 11, wherein the decision feedback equalizer further comprises:

a first summer circuit configured to sum the equalized input signal with a first plurality of signals and to output a first internal signal, wherein the first summer circuit comprises a first switch disposed between the first summer circuit and a voltage source, and wherein the first summer circuit is disposed in the high path;

a second summer circuit configured to sum the equalized input signal with a second plurality of signals and to output a second internal signal, wherein the second summer circuit comprises a second switch disposed between the second summer circuit and the voltage source, and wherein the second summer circuit is disposed in the low path; and

a multiplexer configured to receive the first internal signal and the second internal signal and to provide one of the first internal signal and the second internal signal at an output of the multiplexer;

wherein logic circuitry is configured to disable the low path by controlling the second switch to disconnect the second summer circuit from the voltage source; and

and wherein the logic circuitry is configured to provide the equalized input signal as the output signal by controlling the multiplexer to provide only the first internal signal at the output of the multiplexer.

13. A method for equalizing an input signal using a decision feedback equalizer, the method comprising:

receiving, with logic circuitry, an

indication to use the decision feedback equalizer in one of a plurality of modes; and

in response to the indication;

providing an input signal to a first summer circuit in the decision feedback equalizer;

disabling, with the logic circuitry, a second summer circuit coupled to the first summer circuit in the decision feedback equalizer; and

configuring, with the logic circuitry, a multiplexer coupled to the first summer circuit and the second summer circuit to select a signal generated by the first summer circuit for output.

14. The method of claim 13, wherein the indicated mode is one of a high path calibration mode and a bypass mode.

15. The method of claim 13 further comprising, in response to the indication, disabling a plurality of delay circuits coupled to the multiplexer.

16. The method of claim 13 further comprising:

receiving, with logic circuitry, a second indication to use the decision feedback equalizer in a second of the plurality of modes; and

in response to the second indication;

enabling, with the logic circuitry, the second summer circuit;

providing the input signal to the first summer circuit and the second summer circuit; and

configuring the multiplexer, with the logic circuitry, to select one of the signal generated by the first summer circuit and a signal generated by the second summer circuit for output depending on a clock signal and first and second feedback signals.

17. The method of claim 13 further comprising:

receiving, with logic circuitry, a second indication to use the decision feedback equalizer in a second of the plurality of modes; and

in response to the second indication;

enabling the second summer circuit, with the logic circuitry, and providing the input signal to the second summer circuit;

disabling the first summer circuit with the logic circuitry; and

configuring the multiplexer, with the logic circuitry, to select a signal generated by the second summer circuit for output.

18. The method of claim 13 further comprising:

varying a control signal to control a current source in the first summer circuit;

monitoring the signal generated by the first summer circuit in response to the varying;

detecting an optimal offset cancellation level based on the monitoring; and

storing an indication of the control signal as calibration data when the optimal offset cancellation level is detected.

19. The method of claim 18 further comprising, in response to a second indication of a second of the plurality of modes, retrieving the stored calibration data and setting the control signal based on the retrieved calibration data.

20. The method of claim 13, further comprising, in response to the indication, generating a control signal with the logic circuitry, wherein the control signal disables a plurality of current sources in the first summer circuit.