Techniques for generating fractional periodic signals

• US 8,537,956 B1
• Filed: 11/24/2010
• Issued: 09/17/2013
• Est. Priority Date: 11/24/2010
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Pham, Tien Duc, Shumarayev, Sergey, Ekas, Paul B., Zheng, Leon, Wong, Zhi Y.
• Primary Examiner(s): LAM, KENNETH T
• Application Number:
  US12/954,514
• Time in Patent Office: 1,028 Days
• Field of Search: 375/376, 375/373, 375/371, 375/354, 375/316
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits
• CPC Class Codes: H04J 3/062 Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06

Abstract

A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.

Claims

1. A circuit comprising:

a fractional phase-locked loop circuit comprising phase detection circuitry, an oscillator circuit that generates a first periodic signal, and a frequency divider circuit that divides a frequency of the first periodic signal by a frequency division value to generate a frequency of a second periodic signal, wherein the second periodic signal is provided to the phase detection circuitry; and

a delta sigma modulator circuit comprising a first accumulator that performs a first addition, first storage circuits that store signals based on the first addition received from the first accumulator, a first multiplexer that receives the signals based on the first addition from the first storage circuits and that provides one of the signals based on the first addition as a first selected signal, and a logic circuit that controls the frequency division value based on the first selected signal.

2. The circuit of claim 1 wherein the delta sigma modulator circuit further comprises a second accumulator that performs a second addition, second storage circuits that store signals based on the second addition received from the second accumulator, a second multiplexer that receives the signals based on the second addition from the second storage circuits and that provides one of the signals based on the second addition as a second selected signal, wherein the logic circuit controls the frequency division value based on the first and the second selected signals.

3. The circuit of claim 2 further comprising:

a linear feedback shift register that generates a carry in signal, wherein the second accumulator performs the second addition based on the carry in signal.

4. The circuit of claim 2 wherein the signals based on the first addition are provided from the first storage circuits to multiplexing inputs of the first multiplexer, to inputs of the first accumulator and to first inputs of the second accumulator, and wherein the signals based on the second addition are provided from the second storage circuits to multiplexing inputs of the second multiplexer and to second inputs of the second accumulator.

5. The circuit of claim 4 wherein the first storage circuits store a prime number in response to first preset signals and the second storage circuits store a prime number in response to second preset signals.

6. The circuit of claim 4 wherein the delta sigma modulator circuit further comprises a third accumulator that performs a third addition, a third multiplexer that receives signals based on the third addition and that provides one of the signals based on the third addition as a third selected signal, wherein the logic circuit controls the frequency division value based on the first, the second, and the third selected signals.

7. The circuit of claim 6 wherein the delta sigma modulator circuit further comprises third storage circuits that store the signals based on the third addition, wherein the signals based on the third addition are provided from the third storage circuits to multiplexing inputs of the third multiplexer and to first inputs of the third accumulator, and wherein the signals based on the second addition are provided from the second storage circuits to second inputs of the third accumulator.

8. The circuit of claim 2 wherein the first multiplexer receives at a multiplexing input a first overflow signal generated by the first accumulator from the first addition, and wherein the second multiplexer receives at a multiplexing input a second overflow signal generated by the second accumulator from the second addition.

9. The circuit of claim 1 wherein the first multiplexer receives signals indicating a sum of the first addition, and wherein the first multiplexer provides a different one of the signals indicating the sum of the first addition as the first selected signal to adjust a precision of an average frequency of the first periodic signal.

10. The circuit of claim 1 wherein a third periodic signal is provided to the phase detection circuitry, and wherein the first periodic signal has an average frequency that equals a frequency of the third periodic signal times a fractional, non-integer number.

11. A method comprising:

generating a first periodic signal using an oscillator circuit;

dividing a frequency of the first periodic signal by a frequency division value to generate a frequency of a second periodic signal using a frequency divider circuit;

providing the second periodic signal to phase detection circuitry, wherein the oscillator circuit, the frequency divider circuit, and the phase detection circuitry are part of a fractional phase-locked loop circuit;

performing a first addition using a first accumulator;

receiving signals that indicate a sum of the first addition at a first multiplexer and providing one of the signals that indicate the sum of the first addition as a first selected signal;

controlling the frequency division value based on the first selected signal using a logic circuit, wherein the first accumulator, the first multiplexer, and the logic circuit are part of a delta sigma modulator circuit; and

changing the one of the signals that indicate the sum of the first addition provided by the first multiplexer as the first selected signal to adjust a precision of an average frequency of the first periodic signal.

12. The method of claim 11 further comprising:

performing a second addition using a second accumulator; and

receiving signals that indicate a sum of the second addition at a second multiplexer and providing one of the signals that indicate the sum of the second addition as a second selected signal,

wherein changing the one of the signals that indicate the sum of the first addition provided by the first multiplexer as the first selected signal to adjust a precision of an average frequency of the first periodic signal further comprises changing the one of the signals that indicate the sum of the second addition provided by the second multiplexer as the second selected signal to adjust the precision of the average frequency of the first periodic signal, and

wherein controlling the frequency division value based on the first selected signal using a logic circuit comprises controlling the frequency division value based on the first and the second selected signals, and wherein the second accumulator and the second multiplexer are part of the delta sigma modulator circuit.

13. The method of claim 12 further comprising:

generating a carry in signal using a linear feedback shift register, wherein performing a second addition using a second accumulator comprises performing the second addition based on the carry in signal.

14. The method of claim 12 further comprising:

storing the signals that indicate the sum of the first addition in first storage circuits;

storing the signals that indicate the sum of the second addition in second storage circuits;

providing the signals that indicate the sum of the first addition from the first storage circuits to multiplexing inputs of the first multiplexer, to inputs of the first accumulator, and to first inputs of the second accumulator; and

providing the signals that indicate the sum of the second addition from the second storage circuits to multiplexing inputs of the second multiplexer and to second inputs of the second accumulator, wherein the first storage circuits and the second storage circuits are part of the delta sigma modulator circuit.

15. The method of claim 14 further comprising:

storing a prime number that is greater than one in the first storage circuits in response to first preset signals; and

storing a prime number that is greater than one in the second storage circuits in response to second preset signals.

16. The method of claim 14 further comprising:

performing a third addition using a third accumulator; and

receiving signals that indicate a sum of the third addition at a third multiplexer and providing one of the signals that indicate the sum of the third addition as a third selected signal,

wherein changing the one of the signals that indicate the sum of the first addition provided by the first multiplexer as the first selected signal to adjust a precision of an average frequency of the first periodic signal further comprises changing the one of the signals that indicate the sum of the third addition provided by the third multiplexer as the third selected signal to adjust the precision of the average frequency of the first periodic signal,

wherein controlling the frequency division value based on the first selected signal using a logic circuit comprises controlling the frequency division value based on the first, the second, and the third selected signals, wherein the third accumulator and the third multiplexer are part of the delta sigma modulator circuit.

17. The method of claim 16 further comprising:

storing the signals that indicate the sum of the third addition in third storage circuits;

providing the signals that indicate the sum of the third addition from the third storage circuits to multiplexing inputs of the third multiplexer and to first inputs of the third accumulator; and

providing the signals that indicate the sum of the second addition from the second storage circuits to second inputs of the third accumulator, wherein the third storage circuits are part of the delta sigma modulator circuit.

18. The method of claim 12 further comprising:

receiving a first overflow signal generated by the first accumulator from the first addition at a multiplexing input of the first multiplexer; and

receiving a second overflow signal generated by the second accumulator from the second addition at a multiplexing input of the second multiplexer.

19. The method of claim 11 further comprising:

providing a third periodic signal to the phase detection circuitry, wherein the average frequency of the first periodic signal equals a frequency of the third periodic signal times a fractional, non-integer number.

20. A circuit comprising:

a fractional phase-locked loop circuit comprising phase detection circuitry, an oscillator circuit that generates a first periodic signal, and a frequency divider circuit that divides a frequency of the first periodic signal by a frequency division value to generate a frequency of a second periodic signal, wherein the second periodic signal is provided to the phase detection circuitry; and

a delta sigma modulator circuit comprising a first accumulator that performs a first addition, a first multiplexer that receives signals based on the first addition and that provides one of the signals based on the first addition as a first selected signal, a second accumulator that performs a second addition, a second multiplexer that receives signals based on the second addition and that provides one of the signals based on the second addition as a second selected signal, and a logic circuit that generates the frequency division value by performing a mathematical function on values of the first and the second selected signals.