Performing AES encryption or decryption in multiple modes with a single instruction

• US 8,538,012 B2
• Filed: 03/14/2007
• Issued: 09/17/2013
• Est. Priority Date: 03/14/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dixon, Martin, Chennupaty, Srinivas, Gueron, Shay
• Primary Examiner(s): Orgad, Edan
• Assistant Examiner(s): Baum, Ronald
• Application Number:
  US11/724,005
• Publication Number:
  US 20080229116A1
• Time in Patent Office: 2,379 Days
• Field of Search: 380/28
• US Class Current: 380/28
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0637 Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]

Abstract

A machine-readable medium may have stored thereon an instruction, which when executed by a machine causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction.

Claims

1. A machine-readable non-transitory storage medium having stored thereon an instruction, which when executed by a machine causes the machine to perform a method comprising:

determining from a first operand of the instruction an Advanced Encryption Standard (AES) encryption mode by which to encrypt data;

applying an exclusive OR operation to the first operand of the instruction and a second operand of the instruction to produce a combined result and encrypting the combined result using a key in accordance with the determined AES encryption mode to produce an encrypted result; and

placing the encrypted result in a memory location of the first operand of the instruction.

2. The medium of claim 1, wherein the encrypting includes:

obtaining the key from one or more predetermined registers.

3. The medium of claim 2, wherein the key is 128 bits or 256 bits in length.

4. The medium of claim 1, wherein the second operand is plaintext to be encrypted that is 128 bits in length.

5. The medium of claim 1, wherein the first operand is zero in a first AES encryption mode by which the result is encrypted.

6. The medium of claim 1, wherein the first operand is a prior encrypted result from a prior encryption operation in a second AES encryption mode by which the result is encrypted.

7. A processor to perform encryption, comprising:

a first logic, responsive to execution of a single instruction that includes a first operand and a second operand and executable in a selected one of a plurality of Advanced Encryption Standard (AES) modes, to logically combine, via an exclusive OR operation (XOR), a plaintext value supplied by the second operand with a second value supplied by the first operand to produce a combined result, and to encrypt the combined result using an AES algorithm and a key to produce an encrypted result, wherein a particular mode of the plurality of the AES modes via which to produce the encrypted result is selected according to the first operand.

8. The processor of claim 7, further comprising:

a first register to store the second value; and

a second register to store the key.

9. The processor of claim 8, wherein the first logic is arranged to store the encrypted result in the first register.

10. The processor of claim 7, wherein the second value of zero is distinctly associated with a first mode of encryption and the second value of a previously encrypted result is distinctly associated with a second mode of encryption.

11. The processor of claim 7, wherein the plaintext value and the encrypted result are each 128 bits in length.

12. A system to encrypt data, comprising:

a memory to store an Advanced Encryption Standard (AES) encryption instruction having two operands; and

a processor to execute the AES encryption instruction according to a particular mode of a plurality of modes of the AES encryption instruction, the particular mode determined based on a value of one of the two operands, wherein;

in a first mode and responsive to execution of the AES encryption instruction, the

processor is to execute a first loop to clear a first operand, logically combine a plaintext value supplied by a second operand obtained from a first corresponding memory location of a first memory, the first corresponding memory location indicated by a counter value, with a second value supplied by the first operand to produce a combined result, encrypt the combined result using an AES algorithm and a key to produce an encrypted result, store the encrypted result in a second corresponding memory location of a second memory, the second corresponding memory location indicated by the counter value, decrement the counter value, and re-execute the first loop until the counter value reaches a predetermined value; and

in a second mode and responsive to the execution of the AES encryption instruction, the processor is to clear the first operand, and thereafter execute a second loop to logically combine the plaintext value with the second value to produce the combined result, encrypt the combined result using the AES algorithm and the key to produce the encrypted result, store the encrypted result in the second corresponding memory location of the second memory indicated by the counter value, decrement the counter value, and re-execute the second loop until the counter value reaches the predetermined value.

13. The system of claim 12, wherein the AES encryption instruction has only two operands.

14. The system of claim 12, wherein the at least two modes includes two of electronic codebook mode, counter mode, and cipher block chaining mode.

15. The system of claim 12, wherein when a first operand has a value of zero, the selected mode is electronic codebook (EBC).

16. The system of claim 12, wherein the plaintext value is logically combined with the second value via an XOR operation.