Flexible architecture and instruction for advanced encryption standard (AES)

• US 8,538,015 B2
• Filed: 03/28/2007
• Issued: 09/17/2013
• Est. Priority Date: 03/28/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gueron, Shay, Feghali, Wajdi K., Gopal, Vinodh, Raghunandan, Makaram, Dixon, Martin G., Chennupaty, Srinivas, Kounavis, Michael E.
• Primary Examiner(s): Patel, Ashok
• Assistant Examiner(s): Mangialaschi, Tracy
• Application Number:
  US11/729,199
• Publication Number:
  US 20080240426A1
• Time in Patent Office: 2,365 Days
• Field of Search: 380/28, 380/44
• US Class Current: 380/44
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/402 Encrypted data
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/454 Vector or matrix data
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 3/0623 in relation to content
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30178 of compressed or encrypted instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3818 Decoding for concurrent execution
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3895 : for complex operations, e.g. multidimensional or interleaved address generators, macros
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H04L 2209/12 : Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/24 : Key scheduling, i.e. generating round keys or sub-keys for block encryption
• CPC Class Codes: H04L 9/0631 : Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0816 : Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
• CPC Class Codes: H04L 9/0861 : Generation of secret information including derivation or calculation of cryptographic keys or passwords

Abstract

A flexible instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Claims

1. An apparatus comprising:

a microprocessor, the microprocessor comprising;

an execution unit, the execution unit comprising a plurality of execution ports, each execution port having an execution port number;

a key scheduler, the key scheduler to generate a round key for an Advanced Encryption Standard (AES) round associated with an AES round key operation based on a received key;

AES round logic to perform one AES round operation to compute a result of an AES round instruction, the AES round instruction including a first operand to provide an input state and a second operand to provide the round key for the AES round operation, the result stored in a register file to provide the input state for a next AES round instruction or a last AES round instruction; and

wherein the AES round logic issues the AES round instruction to a specified execution port number of the execution unit.

2. The apparatus of claim 1, wherein the round key is stored in a data cache and each of the AES round instruction and the last AES round instruction has a unique operation code.

3. The apparatus of claim 2, wherein an AES round operation to cause the execution unit to:

perform an exclusive OR (XOR) operation on an input to the round and the round key for the AES round to produce an intermediate value;

perform a substitution operation for each byte in the intermediate value based on values stored in a lookup table; and

pass results of the substitution operation through a bit-linear transform that shifts rows in the intermediate value.

4. The apparatus of claim 1, wherein an AES round operation for the AES round instruction to cause the execution unit to:

perform an exclusive OR (XOR) operation on the input to the AES round and the round key for the AES round to produce an intermediate value;

perform a substitution operation for each byte in the intermediate value based on values stored in a lookup table;

pass results of the substitution operation through a bit-linear transform that shifts rows in the intermediate value; and

pass results of the substitution operation through bit linear transform that mixes columns in the intermediate value.

5. The apparatus of claim 1, wherein an AES round operation for the last round instruction to cause the execution unit to:

perform an exclusive OR (XOR) operation on an input to the round and the round key for the AES round to produce an intermediate value;

perform a substitution operation for each byte in the intermediate value based on values stored in a lookup table; and

pass results of the substitution operation through a bit-linear transform that shifts rows in the intermediate value.

6. The apparatus of claim 1, wherein the result is an encrypted value.

7. The apparatus of claim 1, wherein the result is a decrypted value.

8. The apparatus of claim 1, wherein the round key and the input state for the AES round instruction are stored in a register of the register file.

9. The apparatus of claim 8, wherein the register file includes a plurality of 128-bit registers.

10. A method comprising:

generating a round key for an Advanced Encryption Standard (AES) round associated with an AES round key operation based on a received key;

performing one AES round operation to compute a result of an AES round instruction, the AES instruction including a first operand to provide an input state and a second operand to provide the round key for the AES round operation, the result stored in a register file to provide the input state for a next AES round instruction or a last AES round instruction; and

issuing the AES round instruction to a specified execution port number of an execution unit, wherein the execution unit comprises a plurality of execution ports, each execution port having an execution port number.

11. The method of claim 10, further comprising:

storing the generated round key in a data cache and each of the AES round instruction and the last AES round instruction has a unique operation code.

12. The method of claim 10, wherein performing the AES round operation comprises:

performing an exclusive OR (XOR) operation on an input to the round and the round key for the AES round to produce an intermediate value;

performing a substitution operation for each byte in the intermediate value based on values stored in a lookup table; and

passing results of the substitution operation through a bit-linear transform that shifts rows in the intermediate value.

13. The method of claim 10, wherein performing the AES round instruction comprises:

performing an exclusive OR (XOR) operation on the input to the AES round and the round key for the AES round to produce an intermediate value;

performing a substitution operation for each byte in the intermediate value based on values stored in a lookup table;

passing results of the substitution operation through a bit-linear transform that shifts rows in the intermediate value; and

passing results of the substitution operation through bit linear transform that mixes columns in the intermediate value.

14. The method of claim 10, wherein performing the last AES round instruction comprises:

performing an exclusive OR (XOR) operation on an input to the round and the round key for the AES round to produce an intermediate value;

performing a substitution operation for each byte in the intermediate value based on values stored in a lookup table; and

passing results of the substitution operation through a bit-linear transform that shifts rows in the intermediate value.

15. The method of claim 10, wherein the result is an encrypted value.

16. The method of claim 10, wherein the result is a decrypted value.

17. The method of claim 10, wherein the round key and the input state for the AES round instruction are stored in a register of the register file.

18. The method of claim 17, wherein the register file includes a plurality of 128-bit registers.

19. A computer usable non-transitory medium including a computer readable code stored thereon having instructions, wherein the instructions, when executed by a microprocessor, results in a machine performing:

generating a round key for an Advanced Encryption Standard (AES) round associated with an AES round key operation based on a received key;

performing one AES round operation to compute a result of an AES round instruction, the AES instruction including a first operand to provide an input state and a second operand to provide the round key for the AES round operation, the result stored in a register file to provide the input state for a next AES round instruction or a last AES round instruction; and

issuing the AES round instruction to a specified execution port number of an execution unit, wherein the execution unit comprises a plurality of execution ports, each execution port having an execution port number.

20. The computer usable medium of claim 19, further comprising:

storing the generated round key in a data cache and each of the AES round instruction and the last AES round instruction has a unique operation code.

21. The computer usable medium of claim 19, wherein if the number of AES rounds is equal to 1, prior to performing the sequence of AES round operations, loading a pre-computed round key for the AES round based on the key.

22. A system comprising:

a dynamic random access memory to store data and instructions; and

a microprocessor coupled to said memory to execute the instructions, the microprocessor comprising;

an execution unit, the execution unit comprising a plurality of execution ports, each execution port having an execution port number;

a key scheduler, the key scheduler to generate a round key for an Advanced Encryption Standard (AES) round associated with an AES round key operation based on a received key;

AES round logic to perform one AES round operation to compute a result of an AES round instruction, the AES round instruction including a first operand to provide an input state and a second operand to provide the round key for the AES round operation, the result stored in a register file to provide the input state for a next AES round instruction or a last AES round instruction; and

wherein the AES round logic issues the AES round instruction to a specified execution port number of the execution unit.

23. The system of claim 22, wherein the round key is stored in a data cache and each of the AES round instruction and the last AES round instruction has a unique operation code.