Buffer circuit with integrated loss canceling
First Claim
1. A filter circuit, comprising:
- a first buffered filtering stage includinga first Q-deficient filter stage to receive an input signal; and
a first Q-enhancement buffer stage coupled to-the first Q-deficient filter stage, wherein the first Q-enhancement buffer stage includes a single active device to increase a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from any subsequent filter stage.
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Accused Products
Abstract
A filter circuit enhances a deficient Q-value in a filter stage and buffers the filter stage from subsequent filter stages using a common active device. A filter circuit includes a first buffered filtering stage including a first Q-deficient filter stage to receive an input signal and a first Q-enhancement buffer stage. The first Q-enhancement buffer stage is coupled to the first Q-deficient filter stage, wherein the first Q-enhancement buffer stage includes a single active device to increase a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from any subsequent filter stage. A filtering method includes filtering an input signal in a first Q-deficient filter stage and enhancing a deficient Q-value of the first Q-deficient filter stage with an active device. The method further includes buffering the first Q-deficient filter stage from any subsequent filter stage with the active device.
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Citations
20 Claims
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1. A filter circuit, comprising:
a first buffered filtering stage including a first Q-deficient filter stage to receive an input signal; and a first Q-enhancement buffer stage coupled to-the first Q-deficient filter stage, wherein the first Q-enhancement buffer stage includes a single active device to increase a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from any subsequent filter stage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A filter circuit, comprising:
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a first Q-deficient filter stage; a second filter stage; and a first Q-enhancement buffer stage coupled therebetween, the first Q-enhancement buffer stage configured to enhance a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from the second filter stage using a single active device. - View Dependent Claims (10, 11, 12)
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13. A receiver, comprising:
a filter circuit including; a first Q-deficient filter stage; a second filter stage; and a first Q-enhancement buffer stage coupled therebetween, the first Q-enhancement buffer stage configured to enhance a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from the second filter stage using a single active device. - View Dependent Claims (14, 15)
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16. A wireless device, comprising:
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an antenna; and a receiver coupled to the antenna, the receiver including a filter circuit including; a first Q-deficient filter stage; a second filter stage; and a first Q-enhancement buffer stage coupled therebetween, the first Q-enhancement buffer stage configured to enhance a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from the second filter stage using a single active device.
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17. A method, comprising:
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filtering an input signal in a first Q-deficient filter stage; enhancing a deficient Q-value of the first Q-deficient filter stage with an active device; and buffering the first Q-deficient filter stage from any subsequent filter stage with the active device. - View Dependent Claims (18)
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19. A circuit, comprising:
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means for filtering an input signal in a first Q-deficient filter stage; means for enhancing a deficient Q-value of the first Q-deficient filter stage with an active device; and means for buffering the first Q-deficient filter stage from any subsequent filter stage with the active device. - View Dependent Claims (20)
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Specification