Buffer circuit with integrated loss canceling

• US 8,538,367 B2
• Filed: 06/29/2009
• Issued: 09/17/2013
• Est. Priority Date: 06/29/2009
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Nguyen, Cong T., Judson, Bruce A.
• Primary Examiner(s): LE, NHAN T
• Application Number:
  US12/493,568
• Publication Number:
  US 20100330948A1
• Time in Patent Office: 1,541 Days
• Field of Search: 455/307, 455/323, 455/334, 455339-341, 455/550.1, 333172-175
• US Class Current: 455/334
• CPC Class Codes: H03H 11/06 comprising means for compensation of loss
• CPC Class Codes: H03H 7/03 comprising means for compensation of loss
• CPC Class Codes: H03H 7/1775 Parallel LC in shunt or branch path H03H7/1791 takes precedence

Abstract

A filter circuit enhances a deficient Q-value in a filter stage and buffers the filter stage from subsequent filter stages using a common active device. A filter circuit includes a first buffered filtering stage including a first Q-deficient filter stage to receive an input signal and a first Q-enhancement buffer stage. The first Q-enhancement buffer stage is coupled to the first Q-deficient filter stage, wherein the first Q-enhancement buffer stage includes a single active device to increase a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from any subsequent filter stage. A filtering method includes filtering an input signal in a first Q-deficient filter stage and enhancing a deficient Q-value of the first Q-deficient filter stage with an active device. The method further includes buffering the first Q-deficient filter stage from any subsequent filter stage with the active device.

Claims

1. A filter circuit, comprising:

a first buffered filtering stage including

a first Q-deficient filter stage to receive an input signal; and

a first Q-enhancement buffer stage coupled to-the first Q-deficient filter stage, wherein the first Q-enhancement buffer stage includes a single active device to increase a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from any subsequent filter stage.

2. The circuit of claim 1, wherein the first Q-deficient filter stage comprises a resonator configured as one of an LC tank circuit, transmission lines, cavity resonators and acoustic resonators.

3. The circuit of claim 1, wherein the first Q-enhancement buffer stage includes an inductor isolating a collector terminal of the single active device from a power source.

4. The circuit of claim 1, further comprising a second buffered filtering stage including a second filtering stage coupled to the first Q-enhancement buffer stage and isolated from the first Q-deficient filtering stage by the first Q-enhancement buffer stage.

5. The circuit of claim 4, wherein the second filtering stage is a second Q-deficient filter stage and the second filtering stage further includes a second Q-enhancement buffering stage coupled to the second Q-deficient filter stage to increase a Q-value of the second Q-deficient filter stage and isolate the second Q-deficient filter stage from any subsequent filtering stage.

6. The circuit of claim 5, wherein the first buffered filtering stage and the second buffered filtering stage form a respective first pole and a second pole of the filter circuit.

7. The circuit of claim 1, wherein the first Q-enhancement buffer stage is formed as an integrated circuit.

8. The circuit of claim 1, wherein the first Q-deficient filter stage is formed as an integrated circuit.

9. A filter circuit, comprising:

a first Q-deficient filter stage;

a second filter stage; and

a first Q-enhancement buffer stage coupled therebetween, the first Q-enhancement buffer stage configured to enhance a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from the second filter stage using a single active device.

10. The circuit of claim 9, wherein the first Q-enhancement buffer stage is configured as a negative resistance to enhance the Q-value of the first Q-deficient filter stage.

11. The circuit of claim 10, wherein a collector terminal of the active device is isolated from a power source of the first Q-enhancement buffer stage.

12. The circuit of claim 9, wherein the first Q-deficient filter stage and the second filter stage form a respective first pole and a second pole of the filter circuit.

13. A receiver, comprising:

a filter circuit including;

a first Q-deficient filter stage;

a second filter stage; and

a first Q-enhancement buffer stage coupled therebetween, the first Q-enhancement buffer stage configured to enhance a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from the second filter stage using a single active device.

14. The receiver of claim 13, wherein the filter circuit is part of a receiver front-end and the first Q-deficient filter stage

comprises a resonator configured as one of an LC tank circuit, transmission lines, cavity resonators and acoustic resonators.

15. The receiver of claim 13, wherein the first Q-deficient filter stage comprises at least one of an integrated circuit configured as one of an inductor and a capacitor.

16. A wireless device, comprising:

an antenna; and

a receiver coupled to the antenna, the receiver including a filter circuit including;

a first Q-deficient filter stage;

a second filter stage; and

a first Q-enhancement buffer stage coupled therebetween, the first Q-enhancement buffer stage configured to enhance a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from the second filter stage using a single active device.

17. A method, comprising:

filtering an input signal in a first Q-deficient filter stage;

enhancing a deficient Q-value of the first Q-deficient filter stage with an active device; and

buffering the first Q-deficient filter stage from any subsequent filter stage with the active device.

18. The method of claim 17, further comprising isolating the active device from a power source during the enhancing and the buffering.

19. A circuit, comprising:

means for filtering an input signal in a first Q-deficient filter stage;

means for enhancing a deficient Q-value of the first Q-deficient filter stage with an active device; and

means for buffering the first Q-deficient filter stage from any subsequent filter stage with the active device.

20. The circuit of claim 19, further comprising means for isolating the active device from a power source during the enhancing and the buffering.