Device having programmable logic for implementing arithmetic functions

• US 8,539,011 B1
• Filed: 07/19/2007
• Issued: 09/17/2013
• Est. Priority Date: 07/19/2007
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Taylor, Bradley L.
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US11/880,361
• Time in Patent Office: 2,252 Days
• Field of Search: 708/232, 708/523
• US Class Current: 708/232
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A device having programmable logic for implementing arithmetic functions is disclosed. The device comprises an input port coupled to receive a configuration bitstream; a plurality of configurable arithmetic blocks, each configurable arithmetic block comprising configurable circuits for implementing arithmetic functions according to bits of the configuration bitstream; a plurality of input registers coupled to receive multi-bit input words to be processed by the plurality of configurable arithmetic blocks; and an output register enabled to generate an output word. A method of implementing an arithmetic function in a device having programmable logic is also disclosed.

Claims

1. A device having programmable resources for implementing arithmetic functions, the device comprising:

an input port coupled to receive a configuration bitstream; and

a plurality of configurable arithmetic blocks each having a plurality of multiplexers, wherein each multiplexer of the plurality of multiplexers of a configurable arithmetic block is coupled to select a bit of a serial input data stream or a bit of a multiple bit input word based upon the configuration bitstream, and wherein the configurable arithmetic block comprises input registers coupled to outputs of the plurality of multiplexers to receive the multiple bit input word or input bits of the serial input data stream, and comprises an arithmetic function circuit for implementing arithmetic functions on the multiple bit input word according to bits of the configuration bitstream.

2. The device of claim 1 wherein the input registers comprise lookup tables coupled to receive the multiple bit input words.

3. The device of claim 1 further comprising a plurality of output registers coupled to the arithmetic function circuits of the plurality of configurable arithmetic blocks, wherein at least one output register of the plurality of output registers generates a multiple bit output word.

4. The device of claim 3 further comprising a bypass path for coupling, for each configurable arithmetic block, data from an input register of the configurable arithmetic block to an output register.

5. The device of claim 1 wherein each arithmetic function circuit of the plurality of configurable arithmetic blocks comprises a carry-in input and a carry-out output for enabling carry functions between configurable arithmetic blocks.

6. The device of claim 1 wherein each arithmetic function circuit of the plurality of configurable arithmetic blocks comprises an adder extension input and an adder extension output for the sharing of arithmetic function circuits between configurable arithmetic blocks.

7. The device of claim 1 wherein each configurable arithmetic block further comprises an output selection circuit, the output selection circuit coupled to receive data from the arithmetic function circuit or another configurable arithmetic block.

8. A device having programmable resources for implementing arithmetic functions, the device comprising:

a plurality of arithmetic function circuits, each arithmetic function circuit being configurable to implement arithmetic functions according to bits of a configuration bitstream;

a plurality of multiplexers, wherein each multiplexer of the plurality of multiplexers is coupled to select a bit of a serial input data stream or a bit of a multiple bit input word;

a plurality of input registers coupled to outputs of the plurality of multiplexers to receive the multiple bit input word to be processed by an arithmetic function circuit of the plurality of arithmetic function circuits and to receive input bits of a serial input data stream; and

a plurality of output registers coupled to the plurality of arithmetic function circuits, each output register of the plurality of output registers generating a multiple bit output word.

9. The device of claim 8 further comprising an output selection circuit coupled to an arithmetic function circuit of the plurality of arithmetic function circuits and an input register of the plurality of input registers, wherein the output selection circuit enables the selection of data from either the arithmetic function circuit or the input register.

10. The device of claim 9 wherein the output selection circuit receives data from another arithmetic function circuit of the plurality of arithmetic function circuits by way of a data input and couples data to another arithmetic function circuit of the plurality of arithmetic function circuits by way of a data output.

11. The device of claim 8 wherein the plurality of input registers comprises a plurality of configurable lookup tables, each lookup table being configurable to generate a single bit output or a multiple bit output word.

12. The device of claim 11 wherein each lookup table further comprises a programmable shift register.

13. The device of claim 8 wherein each arithmetic function circuit of the plurality of arithmetic function circuits comprises adder circuits which are programmably interconnected according to data stored in configuration memory elements.

14. The device of claim 13 wherein each arithmetic function circuit of the plurality of arithmetic function circuits further comprises a multiplier circuit coupled to the plurality of adder circuits.

15. A method of implementing an arithmetic function in a device having programmable resources, the method comprising:

configuring a plurality of configurable arithmetic function circuits, each configurable arithmetic function circuit comprising configurable circuits for implementing arithmetic functions according to bits of a configuration bitstream;

receiving a multiple bit input word;

receiving input bits of a serial input data stream;

enabling the selection of bits of the serial input data stream or bits of the multiple bit input word based upon the configuration bitstream;

coupling selected bits of the multiple bit input word to a configurable arithmetic function circuit of the plurality of configurable arithmetic function circuits;

enabling bypassing, for selected input bits of the serial input data stream, the configurable arithmetic function circuit; and

generating a multiple bit output word.

16. The method of claim 15 wherein generating a multiple bit output word further comprises coupling an output of a configurable arithmetic function circuit to an output selection circuit.

17. The method of claim 16 further comprising coupling a second multiple bit input word to the output selection circuit to bypass the configurable arithmetic function circuit.

18. The method of claim 15 further comprising programming the configurable arithmetic function circuits by way of configuration memory elements.

19. The method of claim 15 further comprising enabling carry functions between pairs of configurable arithmetic function circuits by a carry-in input and a carry-out output.

20. The method of claim 15 further comprising sharing of arithmetic circuits between pairs of configurable arithmetic function circuits by an adder extension input and an adder extension output.