Increasing the number of ranks per channel

• US 8,539,145 B1
• Filed: 07/28/2009
• Issued: 09/17/2013
• Est. Priority Date: 07/28/2009
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Warnes, Lidia, Carr, Dennis, Calhoun, Michael B., Mandle, Aaron R.
• Primary Examiner(s): Sofocleous, Alexander
• Application Number:
  US12/510,822
• Time in Patent Office: 1,512 Days
• Field of Search: None
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer-implemented method for increasing a number of ranks per channel. The channel comprises at least one buffered dual in-line memory module (DIMM). The at least one buffered DIMM comprises a conventional number of ranks and a conventional number of pins. The method includes receiving a memory access request at a memory controller, wherein the memory controller comprises a conventional number of pins. The method also includes encoding a plurality of chip-select (CS) signals at the memory controller, wherein the plurality of CS signals are based on the memory access request, such that the number of ranks per channel increases compared to a conventional number of ranks per channel while not requiring an increase in the number of pins in the memory controller compared to the conventional number of pins of the memory controller.

Claims

1. A computer-implemented method for increasing a number of ranks per channel, wherein said channel comprises at least one buffered dual in-line memory module (DIMM), wherein said at least one buffered DIMM comprises a conventional number of ranks and a conventional number of pins, said method comprising:

receiving, by a computer system, a memory access request at a memory controller, wherein said memory controller comprises a conventional number of pins;

encoding, by said computer system, a plurality of chip-select (CS) signals at said memory controller, wherein said plurality of CS signals are based on said memory access request, such that said number of ranks per said channel increases compared to a conventional number of ranks per said channel while not requiring an increase in said number of pins in said memory controller compared to said conventional number of pins of said memory controller;

reducing, by said computer system, a number of on-die-termination (ODT) pins needed at said at least one said buffered DIMM compared to a conventional number of ODT pins needed at said at least one said buffered DIMM based on a combination of CS and ODT encoding and DIMM Inter-Integrated Circuit (I²C) address bits, wherein a buffer on said buffered DIMM is assigned a unique address based upon a DIMM I²C address assigned to the slot in which said buffered DIMM is installed, and wherein said buffer is programmed on boot-up to decode a subset of received CS signals based at least in part on said unique address; and

reducing, by said computer system, a number of clock-enable (CKE) pins needed at said at least one said buffered DIMM compared to a conventional number of CKE pins needed at said at least one said buffered DIMM based on said combination of CS and ODT encoding and DIMM Inter-Integrated Circuit (I²C) address bits.

2. The computer-implemented method of claim 1, wherein said method comprises:

encoding a single on-die-termination (ODT) signal and a single clock-enable (CKE) signal at said memory controller for said increase in said number of ranks per said channel.

3. The computer-implemented method of claim 1, wherein said encoding a plurality of CS signals comprises:

encoding a reduced plurality of CS signals at said memory controller, wherein said reduced plurality of CS signals is less than a conventional plurality of CS signals.

4. The computer-implemented method of claim 1, wherein said plurality of chip-select (CS) signals comprises bussed, multi-stub unidirectional signals.

5. A computer-implemented method for increasing a number of ranks per channel, wherein said channel comprises at least one buffered dual in-line memory module (DIMM), wherein said at least one buffered DIMM comprises a conventional number of ranks and a conventional number of pins, said method comprising:

receiving, by a computer system, a plurality of encoded chip-select (CS) signals at a buffer of said at least one buffered DIMM;

decoding, by said computer system, said plurality of CS signals at said buffer of said at least one buffered DIMM, such that said number of ranks per said channel increases compared to a conventional number of ranks per said channel while not requiring an increase in said number of pins in said at least one buffered DIMM compared to said conventional number of pins of said at least one buffered DIMM;

reducing, by said computer system, a number of on-die-termination (ODT) pins needed at said at least one said buffered DIMM compared to a conventional number of ODT pins needed at said at least one said buffered DIMM based on a combination of CS and ODT encoding and DIMM Inter-Integrated Circuit (I²C) address bits, wherein a buffer on said buffered DIMM is assigned a unique address based upon a DIMM I²C address assigned to the slot in which said buffered DIMM is installed, and wherein said buffer is programmed on boot-up to decode a subset of received CS signals based at least in part on said unique address; and

reducing, by said computer system, a number of clock-enable (CKE) pins needed at said at least one said buffered DIMM compared to a conventional number of CKE pins needed at said at least one said buffered DIMM based on said combination of CS and ODT encoding and DIMM Inter-Integrated Circuit (I²C) address bits.

6. The computer-implemented method of claim 5, wherein said method comprises:

decoding a single on-die-termination (ODT) signal at said buffer of said at least one buffered DIMM for said increase in said number of ranks per said channel.

7. The computer-implemented method of claim 5, wherein said method comprises:

decoding a single clock-enable (CKE) signal at said buffer of said at least one buffered DIMM for said increase in said number of ranks per said buffered channel.

8. The computer-implemented method of claim 5, wherein said method comprises:

receiving said plurality of encoded CS signals at every buffer of a plurality of DIMMs, wherein said at least one DIMM is said plurality of DIMMs; and

decoding said plurality of encoded CS signals at said every buffer of said plurality of DIMMs, such that said number of ranks per said channel increases compared to a conventional number of ranks per said channel while not requiring an increase in the number of pins in said plurality of buffered DIMMs compared to a conventional number of pins of said plurality of buffered DIMMs.

9. The computer-implemented method of claim 5, wherein said method comprises:

determining, if said plurality of CS signals belong to said at least one buffered DIMM based upon a unique identifier assigned to a buffer comprised within said DIMM based upon DIMM Inter-Integrated Circuit (I²C) address bits.

10. The computer-implemented method of claim 5, wherein said method comprises:

decoding a maximum number of CS signals conventionally allowed for said memory access of said at said buffer of said at least one DIMM;

decoding a single on-die-termination (ODT) signal at said buffer of said at least one said buffered DIMM; and

decoding a single clock-enable (CKE) signal at said buffer of said at least one said buffered DIMM.

11. The computer-implemented method of claim 5, wherein said method comprises:

increasing said number of ranks per channel to at least 32 ranks per channel.

12. A computer-implemented method for increasing a number of ranks per channel, wherein said channel comprises at least one buffered dual in-line memory module (DIMM), wherein said at least one buffered DIMM comprises a conventional number of ranks and a conventional number of pins, said method comprising:

receiving, by a computer system, a memory access request at a memory controller, wherein said memory controller comprises a conventional number of pins;

encoding, by said computer system, a plurality of chip-select (CS) signals at said memory controller, wherein said chip select signals are based on said memory access request;

decoding, by said computer system, said plurality of CS signals at a buffer of said at least one buffered DIMM, such that said number of ranks per said channel increases compared to a conventional number of ranks per said channel while not requiring an increase in said number of pins in said at least one buffered DIMM compared to said conventional number of pins of said at least one buffered DIMM and not requiring an increase in the number of pins in said memory controller compared to said conventional number of pins of said memory controller;

reducing, by said computer system, a number of on-die-termination (ODT) pins needed at said at least one said buffered DIMM compared to a conventional number of ODT pins needed at said at least one said buffered DIMM based on a combination of CS and ODT encoding and DIMM Inter-Integrated Circuit (I²C) address bits, wherein a buffer on said buffered DIMM is assigned a unique address based upon a DIMM I²C address assigned to the slot in which said buffered DIMM is installed, and wherein said buffer is programmed on boot-up to decode a subset of received CS signals based at least in part on said unique address; and

reducing, by said computer system, a number of ODT pins needed at said memory controller compared to a conventional number of ODT pins needed at said memory controller DIMM based on the combination of said CS and ODT encoding and said DIMM I²C address bits.

13. The computer-implemented method of claim 12, wherein said method comprises:

encoding a single on-die-termination (ODT) signal at said memory controller and decoding said single ODT signal at said buffer of said at least one buffered DIMM, wherein said single ODT is based on said memory access request; and

encoding a single clock-enable (CKE) signal at said memory controller and decoding said signal CKE at said buffer of said at least one buffered DIMM, wherein said single CKE is based on said memory access request.

14. The computer-implemented method of claim 12, wherein said method comprises:

determining, if said plurality of CS signals belong to said at least one buffered DIMM based upon a unique identifier assigned to a buffer comprised within said DIMM based upon DIMM Inter-Integrated Circuit (I²C) address bits.

15. The computer-implemented method of claim 12, wherein said method comprises:

receiving said plurality of encoded CS signals at every buffer of a plurality of DIMMs, wherein said at least one DI MM is said plurality of DIMMs; and

decoding said plurality of encoded CS signals at said every buffer of said plurality of DIMMs, such that said number of ranks per said channel increases compared to a conventional number of ranks per said channel while not requiring an increase in said number of pins in said plurality of buffered DIMMs compared to a conventional number of pins of said plurality of buffered DIMMs.

16. The computer-implemented method of claim 12, wherein said increasing said ranks per channel comprises:

increasing said ranks per channel to a maximum number of ranks per said channel, wherein said maximum number of ranks per said channel is [2^(number of CS per DIMM)×

((number of CS per channel)/(number of CS per DIMM))].

17. The computer-implemented method of claim 12, wherein said encoding said plurality of CS signals comprises:

encoding a reduced plurality of CS signals at said memory controller, wherein said reduced plurality of CS signals is less than a conventional plurality of CS signals.