Apparatus for scheduling memory refresh operations including power states

• US 8,539,146 B2
• Filed: 11/28/2011
• Issued: 09/17/2013
• Est. Priority Date: 11/28/2011
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brittain, Mark A., Dodson, John Steven, Goodman, Benjiman L., Powell, Stephen J., Stuecheli, Jeffrey A.
• Primary Examiner(s): DOAN, DUC T
• Application Number:
  US13/305,200
• Publication Number:
  US 20130138878A1
• Time in Patent Office: 659 Days
• Field of Search: 711/106
• US Class Current: 711/106
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for performing refresh operations on a rank of memory devices is disclosed. After the completion of a memory operation, a determination is made whether or not a refresh backlog count value is less than a predetermined value and the rank of memory devices is being powered down. If the refresh backlog count value is less than the predetermined value and the rank of memory devices is being powered down, an Idle Count threshold value is set to a maximum value such that a refresh operation will be performed after a maximum delay time. If the refresh backlog count value is not less than the predetermined value or the rank of memory devices is not in a powered down state, the Idle Count threshold value is set based on the slope of an Idle Delay Function such that a refresh operation will be performed accordingly.

Claims

1. A non-transitory computer readable medium having a computer program product for performing refresh operations, said computer readable medium comprising:

program code for, in response to a completion of a memory operation, determining whether or not a refresh backlog count is greater than a first predetermined value;

program code for, in a determination that said refresh backlog count is greater than said first predetermined value, performing a refresh operation as soon as possible;

program code for, in a determination that said refresh backlog count is not greater than said first predetermined value, determining whether or not said refresh backlog count is less than a second predetermined value;

program code for, in a determination that said refresh backlog count is not less than said second predetermined value, determining whether or not said refresh backlog count is less than a third predetermined value and said rank of memory devices is in a powered down state;

program code for, in a determination that said refresh backlog count is less than said third predetermined value and said rank of memory devices is in a powered down state, setting an Idle Count threshold value to a maximum value such that a refresh operation will be performed after a maximum delay time; and

program code for, in a determination that said refresh backlog count is not less than said third predetermined value or said rank of memory devices is not in a powered down state, setting said Idle Count threshold value based on the slope of an Idle Delay Function such that a refresh operation will be performed accordingly.

2. The computer readable medium of claim 1, wherein said first predetermined value is 7.

3. The computer readable medium of claim 1, wherein said second predetermined value is 3.

4. The computer readable medium of claim 1, wherein said third predetermined value is 5.

5. The computer readable medium of claim 1, wherein said idle count value is negatively proportional to said refresh backlog count.

6. The computer readable medium of claim 1, wherein said computer readable medium further includes program code for, in a determination that said refresh backlog count is less than said second predetermined value, setting said Idle Count threshold value to said maximum value.

7. An apparatus for performing refresh operations, said apparatus comprising:

a comparator for, in response to a completion of a memory operation, determining whether or not a refresh backlog count is greater than a first predetermined value; and

a memory controller

for performing a refresh operation as soon as possible, in a determination that said refresh backlog count is greater than said first predetermined value,

for determining whether or not said refresh backlog count is less than a second predetermined value, in a determination that said refresh backlog count is not greater than said first predetermined value,

for determining whether or not said refresh backlog count is less than a third predetermined value and said rank of memory devices is in a powered down state, in a determination that said refresh backlog count is not less than said second predetermined value,

for setting an Idle Count threshold value to a maximum value such that a refresh operation will be performed after a maximum delay time, in a determination that said refresh backlog count is less than said third predetermined value and said rank of memory devices is in a powered down state, and

for setting said Idle Count threshold value based on the slope of an Idle Delay Function such that a refresh operation will be performed accordingly, in a determination that said refresh backlog count is not less than said third predetermined value or said rank of memory devices is not in a powered down state.

8. The apparatus of claim 7, wherein said first predetermined value is 7.

9. The apparatus of claim 7, wherein said second predetermined value is 3.

10. The apparatus of claim 7, wherein said third predetermined value is 5.

11. The apparatus of claim 7, wherein said idle count value is negatively proportional to said refresh backlog count.